Abstract: An interpolative digital-to-analog (D/A) converter is adapted to convert a N-bit digital signal into an analog signal, where N is a positive integer greater than 1. The interpolative D/A converter includes a router unit that outputs first and second router voltages based on the first and second bits of the digital signal, and an interpolation unit that receives the first and second router voltages from the router unit, and that performs interpolation operation on the first and second router voltages according to the first bit of the digital signal, so as to generate the analog signal having a voltage magnitude ranging from the first router voltage to the second router voltage.

Abstract: A method for image data compression of a to-be-encoded image block includes: determining one of a plurality of preset encoding modes as an encoding mode based upon attributes of pixels of the to-be-encoded image block; and compressing image data of the to-be-encoded image block according to the encoding mode thus determined so as to obtain encoded data.

Abstract: A liquid crystal display apparatus includes a liquid crystal panel and a panel driving device. The panel driving device includes a timing control circuit, a gate driving circuit, and a source driving circuit. The source driving circuit includes a low voltage differential signal (LVDS) receiver, a driving voltage generator, and a controller. The LVDS receiver includes a plurality of receive circuits and a power saving control circuit. Each of the receive circuit performs level conversion upon a data LVDS to generate a logic signal, and operates in a selected one of a normal energy consuming mode and a power saving mode. The power saving control circuit controls the receive circuits to operate in the power saving mode when the power saving control circuit does not receive a power adjustment signal from the controller.

Abstract: A temperature sensitive device includes a first delay unit generating a first delayed signal, a second delay unit generating a second delayed signal, a difference generating unit generating an indication signal according to the first delayed signal and the second delayed signal, and a processing unit generating an output signal that is dependent on the temperature sensed by the temperature sensitive device and substantially independent of the manufacturing process of the temperature sensitive device.

Abstract: A display device includes a plurality of pixel circuits arranged in a plurality of rows and columns, a plurality of scan lines, a plurality of data lines, a scan driver operable to drive the rows of the pixel circuits in sequence via the scan lines, and a data driver coupled to the columns of the pixel circuits via the data lines. The scan lines include first and second sets of scan lines alternately disposed with each other. For each of the first and second sets of the scan lines, adjacent scan lines have different circuit properties. The scan driver activates each of the scan lines for a respective activation time period according to the circuit property thereof.

Abstract: A backlight driving circuit includes a scan driver operatively associated with pixel circuits in a matrix formation, and a backlight driver. The scan driver activates the pixel circuits in a row-by-row manner within a frame interval for provision of data voltages to the pixel circuits in each row of the matrix formation, respectively. The backlight driver adjusts a duty cycle of a backlight driving signal for a backlight source such that the backlight source is deactivated when at least one of the pixel circuits is yet to be activated within the frame interval, and adjusts the duty cycle to gradually increase brightness of light output from the backlight source when all of the pixel circuits have been activated within the frame interval.

Abstract: A chip includes: a chip body; and a metal layer formed on the chip body, and including a metal interconnect region electrically connected to the chip body, a light trapping region, and a light reflective region that adjoins the light trapping region and that is able to reflect light. The light trapping region is formed with a plurality of gaps and has a plurality of metal members. Adjacent ones of the metal members are separated by the gaps. Each of the gaps is configured with a width in such a manner that most light irradiating the light trapping region will pass through the gaps and be trapped in the chip body so as to form brightness contrast between the light trapping region and the light reflective region.

Abstract: A dual voltage output circuit includes first and second differential driving units. The first differential driving unit is operable to generate a first output voltage from a pair of first input voltages, has first and second nodes to receive first and second voltage levels, respectively, and has a first intermediate voltage node to receive a first intermediate voltage level. The second differential driving unit is operable to generate a second output voltage from a pair of second input voltages, has third and fourth nodes to receive the first and second voltage levels, respectively, and has a second intermediate voltage node to receive a second intermediate voltage level.

Abstract: A real-time image processing circuit includes: a first converting unit for converting an input image frame into hue data, first saturation data and first luminance data; a saturation processing unit operable to adjust the first saturation data based on saturation mapping information to generate second saturation data corresponding to the input image frame and having a saturation distribution range larger than that of the first saturation data; a luminance processing unit operable to adjust the first luminance data based on luminance mapping information to generate second luminance data corresponding to the input image frame and having a luminance distribution range larger than that of the first luminance data; and a second converting unit for converting the hue data, the second saturation data and the second luminance data into an output image frame corresponding to the input image frame and outputting the output image frame.

Abstract: A differential amplifier circuit includes: P-type and N-type differential input units outputting respectively first and second outputs in response to first and second input voltages; a P-type current mirror circuit driven by the second output; an N-type current mirror circuit driven by the first output; an output unit outputting an output voltage in response to control outputs from the P-type and N-type current mirror circuits; a first sub-current source including first and second P-type transistors connected in series; and a second sub-current source including first and second N-type transistors connected in series. Control ends of the second P-type and second N-type transistors receive the control outputs from the P-type and N-type current mirror circuits, respectively. Control ends of the first P-type and first N-type transistors are coupled to a common node between the first and second P-type transistors, and a common node between the first and second N-type transistors, respectively.

Abstract: A differential amplifier circuit includes: P-type and N-type differential input units outputting respectively first and second outputs in response to first and second input voltages; a P-type current mirror circuit driven by the second output; an N-type current mirror circuit driven by the first output; an output unit outputting an output voltage in response to control outputs from the P-type and N-type current mirror circuits; a first sub-current source including first and second P-type transistors connected in series; and a second sub-current source including first and second N-type transistors connected in series. Control ends of the second P-type and second N-type transistors receive the control outputs from the P-type and N-type current mirror circuits, respectively. Control ends of the first P-type and first N-type transistors are coupled to a common node between the first and second P-type transistors, and a common node between the first and second N-type transistors, respectively.

Abstract: A real-time image processing circuit includes: a first converting unit for converting an input image frame into hue data, first saturation data and first luminance data; a saturation processing unit operable to adjust the first saturation data based on saturation mapping information to generate second saturation data corresponding to the input image frame and having a saturation distribution range larger than that of the first saturation data; a luminance processing unit operable to adjust the first luminance data based on luminance mapping information to generate second luminance data corresponding to the input image frame and having a luminance distribution range larger than that of the first luminance data; and a second converting unit for converting the hue data, the second saturation data and the second luminance data into an output image frame corresponding to the input image frame and outputting the output image frame.

Abstract: A multiplexer includes: a first switch unit coupled between a first input terminal and an output terminal and including a series connection of first and second switches ; a second switch unit coupled between a second input terminal and the output terminal; and a third switch unit coupled to a third input terminal and a common node between the first and second switches. Different first and second voltages, and a third voltage greater than one of the first and second voltages and less than the other one of the first and second voltage are applied respectively to the first, second and third input terminals. The multiplexer is operable between a first mode, where the first voltage is transmitted to the output terminal, and a second mode, where the second voltage is transmitted to the output terminal and the third voltage is transmitted to the common node between the first and second switches.

Abstract: A dual voltage output circuit includes first and second differential driving units. The first differential driving unit is operable to generate a first output voltage from a pair of first input voltages, has first and second nodes to receive first and second voltage levels, respectively, and has a first intermediate voltage node to receive a first intermediate voltage level. The second differential driving unit is operable to generate a second output voltage from a pair of second input voltages, has third and fourth nodes to receive the first and second voltage levels, respectively, and has a second intermediate voltage node to receive a second intermediate voltage level.

Abstract: A data accessing interface between memory and source in LCD display IC includes a multiplex output module and a sequential input module. Suppose a row width of the memory is N bit. The multiplex output module is for outputting a row N-bit digital data. The multiplex output module includes a buffer for receiving the row N-bit digital data from the memory; and a multiplex unit for continuously selecting M bits from the N bit digital data to output to source. After N/M times, all of the row N bit digital data will be output to source. The sequential input module includes N latches and N/M latch control signals; when each latch control signal is active, it will latch M bit digital data from the multiplex output into M latches. After N/M latch control signals are active sequentially, the N bit digital data are stored into the N latches for source.