Patents Assigned to Imagination Technologies
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Patent number: 12086566Abstract: A method of selecting, in hardware logic, an ith largest or a pth smallest number from a set of n m-bit numbers is described. The method is performed iteratively and in the rth iteration, the method comprises: summing an (m?r)th bit from each of the m-bit numbers to generate a summation result and comparing the summation result to a threshold value. Depending upon the outcome of the comparison, the rth bit of the selected number is determined and output and additionally the (m?r?1)th bit of each of the m-bit numbers is selectively updated based on the outcome of the comparison and the value of the (m?r)th bit in the m-bit number. In a first iteration, a most significant bit from each of the m-bit numbers is summed and each subsequent iteration sums bits occupying successive bit positions in their respective numbers.Type: GrantFiled: October 31, 2019Date of Patent: September 10, 2024Assignee: Imagination Technologies LimitedInventor: Thomas Rose
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Patent number: 12086912Abstract: Conservative rasterization hardware comprises hardware logic arranged to perform an edge test calculation for each edge of a primitive and for each corner of each pixel in a microtile. Outer coverage results are determined, for a particular pixel and edge, by combining the edge test results for the four corners of the pixel and the particular edge in an OR gate. Inner coverage results are determined, for a particular pixel and edge, by combining the edge test results for the four corners of the pixel and the particular edge in an AND gate. An overall outer coverage result for the pixel and the primitive is calculated by combining the outer coverage results for the pixel and each of the edges of the primitive in an AND gate. The overall inner coverage result for the pixel is calculated in a similar manner.Type: GrantFiled: June 20, 2023Date of Patent: September 10, 2024Assignee: Imagination Technologies LimitedInventor: Casper Van Benthem
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Patent number: 12079917Abstract: A rendering optimisation identifies a draw call within a current render (which may be the first draw call in the render or a subsequent draw call in the render) and analyses a last shader in the series of shaders used by the draw call to determine whether the last shader samples from the one or more buffers at coordinates matching a current fragment location. If this determination is positive, the method further recompiles the last shader to replace an instruction that reads data from one of the one or more buffers at coordinates matching a current fragment location with an instruction that reads from the one or more buffers at coordinates stored in on-chip registers.Type: GrantFiled: June 23, 2023Date of Patent: September 3, 2024Assignee: Imagination Technologies LimitedInventor: James Glanville
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Patent number: 12073567Abstract: A method of analysing objects in a first frame and a second frame is disclosed. The method includes segmenting the frames, and matching at least one object in the first frame with a corresponding object in the second frame. The method optionally includes estimating the motion of the at least one matched object between the frames. Also disclosed is a method of generating a training dataset suitable for training machine learning algorithms to estimate the motion of objects. Also provided are processing systems configured to carry out these methods.Type: GrantFiled: February 28, 2021Date of Patent: August 27, 2024Assignee: Imagination Technologies LimitedInventors: Aria Ahmadi, David Walton, Cagatay Dikici
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Patent number: 12073593Abstract: A method and decoding unit for decoding a compressed data structure that encodes a set of Haar coefficients for a 2×2 quad of pixels of a block of pixels. The set of Haar coefficients comprises a plurality of differential coefficients and an average coefficient. A first portion of the compressed data structure encodes the differential coefficients for the 2×2 quad of pixels. A second portion of the compressed data structure encodes the average coefficient for the 2×2 quad of pixels. The first portion of the compressed data structure is used to determine signs and exponents differential coefficients which are non-zero. The second portion of the compressed data structure is used to determine a representation of the average coefficient.Type: GrantFiled: July 21, 2022Date of Patent: August 27, 2024Assignee: Imagination Technologies LimitedInventor: Rostam King
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Patent number: 12073612Abstract: A mechanism for performing non-maximum suppression (NMS) on a plurality of detection boxes identifying potential locations for one or more objects within an image. The mechanism uses a tiling system that divides the image into a plurality of tiles. A tile-by-tile suppression process is performed, in which at least some detection boxes that overlap a particular tile are processed to determine whether any detection boxes are to be discarded.Type: GrantFiled: March 19, 2021Date of Patent: August 27, 2024Assignee: Imagination Technologies LimitedInventor: Juraj Mlynar
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Patent number: 12073568Abstract: A data processing device for detecting motion in a sequence of frames each comprising one or more blocks of pixels, includes a sampling unit configured to determine image characteristics at a set of sample points of a block, a feature generation unit configured to form a current feature for the block, the current feature having a plurality of values derived from the sample points, and motion detection logic configured to generate a motion output for a block by comparing the current feature for the block to a learned feature representing historical feature values for the block.Type: GrantFiled: June 13, 2023Date of Patent: August 27, 2024Assignee: Imagination Technologies LimitedInventor: Timothy Smith
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Patent number: 12072833Abstract: An integrated circuit includes a memory configured to store a plurality of functions; a mapping interface configured to perform a mapping from a received first signal to a first function of the plurality of functions; and a state machine configured to, in response to said mapping, execute the first function; wherein the integrated circuit is arranged to, in dependence on the execution of the first function at the state machine, modify said mapping between the first signal and the first function so as to re-map the first signal to a second function of the plurality of functions such that, on receiving a subsequent first signal, the state machine is configured to execute the second function.Type: GrantFiled: June 28, 2022Date of Patent: August 27, 2024Assignee: Imagination Technologies LimitedInventors: Bert Hindle, Ben Fletcher
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Patent number: 12073505Abstract: Ray tracing systems and computer-implemented methods are described for performing intersection testing on a bundle of rays with respect to a box. Silhouette edges of the box are identified from the perspective of the bundle of rays. For each of the identified silhouette edges, components of a vector providing a bound to the bundle of rays are obtained and it is determined whether the vector passes inside or outside of the silhouette edge. Results of determining, for each of the identified silhouette edges, whether the vector passes inside or outside of the silhouette edge, are used to determine an intersection testing result for the bundle of rays with respect to the box.Type: GrantFiled: June 19, 2023Date of Patent: August 27, 2024Assignee: Imagination Technologies LimitedInventors: Gregory Clark, Steven J. Clohset, Luke T. Peterson
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Patent number: 12067681Abstract: Methods and tessellation modules for tessellating a patch to generate tessellated geometry data representing the tessellated patch. Received geometry data representing a patch is processed to identify tessellation factors of the patch. Based on the identified tessellation factors of the patch, tessellation instances to be used in tessellating the patch are determined. The tessellation instances are allocated amongst a plurality of tessellation pipelines that operate in parallel, wherein a respective set of one or more of the tessellation instances is allocated to each of the tessellation pipelines, and wherein each of the tessellation pipelines generates tessellated geometry data associated with the respective allocated set of one or more of the tessellation instances.Type: GrantFiled: June 12, 2023Date of Patent: August 20, 2024Assignee: Imagination Technologies LimitedInventor: John W. Howson
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Patent number: 12061233Abstract: An error detection circuit and method for performing cyclic redundancy check on a clock gated register signal is disclosed. The error detection circuit comprise a first register, a second register, a third register and an error detection module. The first register is a clock gated register and is configured to be updated with a data signal (x) in response to a clock enabling signal. The second register is configured to be updated with a check bit (c) based on the data signal (x). The check bit is calculated by a check bit calculation unit. The third register is configured to be updated with a current value (b) of the clock enabling signal. The error detection module is configured for calculating an indication bit (I) based on at least the output of the first register, the output of the second register and the output of the third register.Type: GrantFiled: March 30, 2023Date of Patent: August 13, 2024Assignee: Imagination Technologies LimitedInventors: Faizan Nazar, Kenneth Rovers
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Patent number: 12061972Abstract: A hardware implementation of a neural network and a method of processing data in such a hardware implementation are disclosed. Input data for a plurality of layers of the network is processed in blocks, to generate respective blocks of output data. The processing proceeds depth-wise through the plurality of layers, evaluating all layers of the plurality of layers for a given block, before proceeding to the next block.Type: GrantFiled: November 30, 2020Date of Patent: August 13, 2024Assignee: Imagination Technologies LimitedInventors: Xiran Huang, Cagatay Dikici
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Patent number: 12056600Abstract: A histogram-based method of selecting a fixed point number format for representing a set of values input to, or output from, a layer of a Deep Neural Network (DNN). The method comprises obtaining a histogram that represents an expected distribution of the set of values of the layer, each bin of the histogram is associated with a frequency value and a representative value in a floating point number format; quantising the representative values according to each of a plurality of potential fixed point number formats; estimating, for each of the plurality of potential fixed point number formats, the total quantisation error based on the frequency values of the histogram and a distance value for each bin that is based on the quantisation of the representative value for that bin; and selecting the fixed point number format associated with the smallest estimated total quantisation error as the optimum fixed point number format for representing the set of values of the layer.Type: GrantFiled: February 8, 2023Date of Patent: August 6, 2024Assignee: Imagination Technologies LimitedInventors: James Imber, Cagatay Dikici
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Patent number: 12056499Abstract: A computer system has a plurality of operating systems, each operating system including a GPU driver; a graphics processing unit (GPU) including GPU firmware for controlling the execution of tasks at the graphics processing unit and, for each operating system: a firmware state register modifiable by the GPU firmware and indicating whether the GPU firmware is online; and an OS state register modifiable by the GPU driver of the respective operating system and indicating whether the GPU driver is online; and a memory management unit configured to mediate access to the registers of the GPU such that each operating system can access its respective registers but not those of other operating systems; wherein: one of the GPU drivers at the plurality of operating systems is a host GPU driver configured to initialise the GPU and bring the GPU firmware online; each GPU driver is configured to submit tasks for processing at the GPU only if its respective firmware state register indicates that the GPU firmware is online;Type: GrantFiled: March 31, 2021Date of Patent: August 6, 2024Assignee: Imagination Technologies LimitedInventors: Mario Sopena Novales, Philip Morris, Mihai Dragan
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Patent number: 12050986Abstract: Hardware for implementing a Deep Neural Network (DNN) having a convolution layer. A plurality of convolution engines are each operable to perform a convolution operation by applying a filter to a data window, each filter comprising a set of weights for combination with respective data values of a data window, and each of the plurality of convolution engines comprising: multiplication logic operable to combine a weight of a filter with a respective data value of a data window; control logic configured to cause the multiplication logic to combine a weight with a respective data value if the weight is non-zero, and otherwise not cause the multiplication logic to combine that weight with that data value; and accumulation logic configured to accumulate the results of a plurality of combinations performed by the multiplication logic so as to form an output for a respective convolution operation.Type: GrantFiled: February 1, 2023Date of Patent: July 30, 2024Assignee: Imagination Technologies LimitedInventor: Christopher Martin
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Patent number: 12051158Abstract: Hardware tessellation units include a sub-division logic block that comprises hardware logic arranged to perform a sub-division of a patch into two (or more) sub-patches. The hardware tessellation units also include a decision logic block that is configured to determine whether a patch is to be sub-divided or not and one or more hardware elements that control the order in which tessellation occurs. In various examples, this hardware element is a patch stack that operates a first-in-last-out scheme and in other examples, there are one or more selection logic blocks that are configured to receive patch data for more than one patch or sub-patch and output the patch data for a selected one of the received patches or sub-patches.Type: GrantFiled: May 1, 2023Date of Patent: July 30, 2024Assignee: Imagination Technologies LimitedInventors: Peter Malcolm Lacey, Simon Fenney
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Patent number: 12051159Abstract: A method and apparatus for rendering a computer-generated image using a stencil buffer is described. The method divides an arbitrary closed polygonal contour into first and higher level primitives, where first level primitives correspond to contiguous vertices in the arbitrary closed polygonal contour and higher level primitives correspond to the end vertices of consecutive primitives of the immediately preceding primitive level. The method reduces the level of overdraw when rendering the arbitrary polygonal contour using a stencil buffer compared to other image space methods. A method of producing the primitives in an interleaved order, with second and higher level primitives being produced before the final first level primitives of the contour, is described which improves cache hit rate by reusing more vertices between primitives as they are produced.Type: GrantFiled: June 2, 2023Date of Patent: July 30, 2024Assignee: Imagination Technologies LimitedInventor: Simon Fenney
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Patent number: 12050849Abstract: A hardware monitor arranged to detect livelock in a hardware design for an integrated circuit. The hardware monitor includes monitor and detection logic configured to detect when a particular state has occurred in an instantiation of the hardware design; and assertion evaluation logic configured to periodically evaluate one or more assertions that assert a formal property related to reoccurrence of the particular state in the instantiation of the hardware design to detect whether the instantiation of the hardware design is in a livelock comprising the predetermined state. The hardware monitor may be used by a formal verification tool to exhaustively verify that the instantiation of the hardware design cannot enter a livelock comprising the predetermined state.Type: GrantFiled: May 19, 2022Date of Patent: July 30, 2024Assignee: Imagination Technologies LimitedInventors: Ashish Darbari, Iain Singleton
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Patent number: 12039667Abstract: A method of generating identifiers (IDs) for primitives and optionally vertices during tessellation. The IDs include a binary sequence of bits that represents the sub-division steps taken during the tessellation process and so encodes the way in which tessellation has been performed. Such an ID may subsequently be used to generate a random primitive or vertex and hence recalculate vertex data for that primitive or vertex.Type: GrantFiled: April 5, 2019Date of Patent: July 16, 2024Assignee: Imagination Technologies LimitedInventor: Peter Malcolm Lacey
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Patent number: 12039643Abstract: The graphics processing unit described herein is configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles. The graphics processing unit comprises a tiling unit and rendering logic. The tiling unit is arranged to generate a tile control list for each tile, the tile control list identifying each graphics data item present in the tile. The rendering logic is arranged to render the tiles using the tile control lists generated by the tiling unit. The tiling unit comprises per-tile hash generation logic arranged to generate, for each tile, a per-tile hash value based on a set of textures that will be accessed when processing the tile in the rendering logic, and the tiling unit is further arranged to store the per-tile hash value for a tile within the tile control list for the tile.Type: GrantFiled: August 4, 2022Date of Patent: July 16, 2024Assignee: Imagination Technologies LimitedInventors: Isuru Herath, Richard Broadhurst