Abstract: A semiconductor coincidence detector device including at least a first and a second detector crystal array, each having a first and second surface, an array of pixellated anodes formed on each of the first surfaces, an array of segmented cathodes formed on each of the second surfaces, essentially each of the pixellated anodes being connected to an anode electronic channel for generating a first electrical signal corresponding to the energy of a photon impinging in the semiconductor, and essentially each of the segmented cathodes being connected to a cathode electronic channel for generating an electrical coincidence trigger signal on detection of a photon impinging in the semiconductor, the first electrical signal being read only from anodes located opposite the cathode segment generating the trigger signal.

Abstract: A signal readout system for a solid state detector array comprising a plurality of detection channels, wherein the decision to output a signal detected by a channel is determined by the content of that channel.

Abstract: A novel semiconductor detector device, consisting of several layers of two dimensional detector modules each module being divided into an array of separate detector cells by means of the pixelation of the electrodes on the surfaces of the modules. The superimposed detector cells in equivalent positions in each layer are in electrical contact with those in the two immediately adjacent layers, such that the whole device effectively becomes a two dimensional array of stacks of individual detector cells, with a common bottom electrode. Current in each detector cell stack, induced by the absorption of a high energy photon in that stack, is measured by means of an integrating charge sensitive amplifier attached to each anode at the top of each cell stack.

Abstract: A semiconductive detector includes a semiconductor substrate having electrodes formed at two opposite-facing surfaces thereof. A peripheral side-wall extends between the two opposite facing-surfaces, and an electrical insulator is formed on at least a portion of the side wall. An electrical conductor is provided over the insulator. A bias voltage may be applied to the conductor such that the electrical insulator and the conductor operate generally in a manner of a field effect transistor.

Abstract: A gamma ray imaging system for providing high resolution images includes a collimator plate with an array of multiple holes which image a gamma emitting object onto a semiconductor gamma detector pixel array coupled to a signal processor. The collimator holes are smaller than half the pixel pitch. The detector array is moved in steps, with a step-size equal to the pitch of the collimator holes, to successive imaging positions. The hole locations and imaging positions are such that gamma photons do not fall on the dead areas of the pixels. An electronic processing unit constructs from the pixel signals produced at each imaging position, a set of independent equations and solves them to derive the exact image signal of each irradiated area, and uses this data to compose and a display a high resolution gamma image of the object.