Abstract: The present invention is directed to a charge pump circuit. A multi-stage charge pump circuit with a particular structure for at least one of said stages is presented. The stage has two switches of which the second switch has a pair of conduction terminals connected between the first control terminal of the first switch and a next stage. The second switch, for instance a transistor, has a second control terminal, the second control terminal being connected to said previous stage. The present charge pump circuit is especially suited for use in an integrated memory device. No special last or output stage is required. Further, the circuit is suited for exploiting the floating well type technology, which is an advantage as the bulk effect is reduced by using such technology. In accordance with a second embodiment of the present invention, the choice of the steering signals (control and node clocks), possibly due to the selecting of the particular stage structure, is discussed.