Abstract: The invention relates to methods of simulation of a plurality of processors running on a plurality of cores, to multi-core microprocessor systems in which such methods may be carried out, and to computer program products configured to perform a simulation of a plurality of processors, running on a plurality of cores. According to a first aspect of the invention, there is provided a method of running a plurality of simulated processors on a plurality of cores, in which simulation of the processors is performed in parallel on the plurality of cores.

Abstract: In a method of simulating a processor system by running code that simulates the system on a host processor, code is translated at run time to a form required by the host processor. All instructions are mapped to a native instruction set of the host using two or more different code dictionaries: the translated instructions are mapped to multiple and different dictionaries dependent on the execution privilege level or mode of the simulated processor. If an instruction is encountered during runtime that changes the mode of the processor the code dictionary is switched to use the dictionary associated with the new mode. The different modes require different instruction mappings to the native instruction set of the host using different models that more accurately represent the behavior of the system code and hardware in the system being simulated.

Abstract: In a method of simulating a processor system by running code that simulates the system on a host processor, code is translated at run time to a form required by the host processor. All instructions are mapped to a native instruction set of the host using two or more different code dictionaries: the translated instructions are mapped to multiple and different dictionaries dependent on the execution privilege level or mode of the simulated processor. If an instruction is encountered during runtime that changes the mode of the processor the code dictionary is switched to use the dictionary associated with the new mode. The different modes require different instruction mappings to the native instruction set of the host using different models that more accurately represent the behaviour of the system code and hardware in the system being simulated.

Abstract: In a method of simulating a multi-processor system by running code that simulates the system on a host processor, a SPECULATE and a COMMIT instruction is used to mark an area of memory, shared across several simulated processors, and the code is translated at run time to a form required by the host processor. All instructions are mapped to a native instruction set of the host using two different code dictionaries: all instructions outside a SPECULATE/COMMIT region are mapped to the first of the two code dictionaries. If a SPECULATE instruction is encountered during runtime by a simulator running the code, the instructions are mapped to a native instruction set of the host using the second code dictionary.