Patents Assigned to Implanted Material Technology, Inc.
  • Patent number: 5589407
    Abstract: The method is a technique for making silicon-on-insulator (SOI) wafers which are suitable for use in the production of CMOS devices, which are designed to operate with low power and low voltage. The method of the invention provides high quality SOI material at relatively low cost by implanting, in one form of the invention, a very low dose of nitrogen or oxygen ions at a very low energy into silicon, and thereafter diffusing oxygen during an annealing process to form a continuous buried layer of silicon-oxy-nitride (Si.sub.x,O.sub.y N.sub.z, or SON) or SiO.sub.2. The process includes using an ion beam to implant ions into the substrate, thereby damaging a region of the crystal. The feed gas for the ion beam may be a variety of nitro-oxide gases, such as NO, N.sub.2 O, NO.sub.2, as well as a simple mixture of nitrogen and oxygen gases. Other elemental ions may be implanted to create the desired crystal defects.
    Type: Grant
    Filed: September 6, 1995
    Date of Patent: December 31, 1996
    Assignee: Implanted Material Technology, Inc.
    Inventors: Narayanan Meyyappan, Tatsuo Nakato