Abstract: An image display system comprises a processor 10, a main memory 20 and a display panel 30, where the main memory 20 includes an uncompressed image area 24 for storing image data relating to an image and a compressed image area 26 for storing compressed image data. The processor is microcode-programmed, and executes, after changes have been made in the uncompressed image area, a special sequence of microcode words in a micro program memory 12 of the processor for compressing at least those parts of the uncompressed image area that are subject to changes. The microcode-compressed parts of the image data are then stored in the compressed image area 26 of the main memory. Compressed image data may then be fetched from the compressed image area 26 and decompressed for enabling generation of an appropriate image signal. The generated image signal can finally be applied to the display 30 for refreshing the image.

Abstract: There is provided a novel microprogrammed processor (100) by combining two or more processor cores (10) in such a way that the processor cores can share the special microprogram memory resource (20) that is located deep inside the processor architecture. In other words, the novel microprogrammed processor (100) basically comprises at least two processor cores (10), and a common internal microprogram control store (20) including microcode instructions for controlling at least the internal standard operation of the multiple processor cores, and suitable means (30) for providing time-shared access to the microprogram control store by the processor cores.

Abstract: Methods and apparatus for creating microcode-implemented peripheral devices for a microcontroller core formed in a monolithic integrated circuit. The microcontroller core has a control store for storing microcode instructions; execution circuitry operable to execute microcode instructions from the control store; and means for loading a suite of one or more microcode-device modules defining an optional peripheral device, the optional peripheral device being implemented by microcode instructions executed by the execution circuitry in accordance with the definition provided by the microcode-device modules.

Abstract: The invention relates to a primary memory such as a dynamic random access memory, and a method and controller for controlling access to such a memory. The access control for the primary memory (60) is intimately associated with the microcode instructions of a processor (10) connected to the memory. The access control is integrated into the microcode program (22) of the processor, and each microcode instruction includes a control instruction used in controlling the operation of a memory controller (50). In the case of a DRAM, the DRAM controller (50) controls access to the DRAM (60) by executing, for each DRAM access, a sequence of DRAM control operations in response to a corresponding sequence of control instructions included in the microcode instructions of the processor.