Abstract: A connector assembly includes a first connector having a connector cover, a head guide formed on the connector cover, an arm guide connected to the connector cover, a first connector body connected to the arm guide, and a connector lever connected to the first connector body. A second connector is slidable along the first connector body and engageable to the connector lever. A slider is slidable along the head guide and the arm guide, and a position of the slider changes by being pressed by the second connector. The slider presses and deforms the connector lever. The connector assembly further includes an elastic body disposed on the arm guide and supporting the slider.

Abstract: The present invention relates to an image output device mounted on a vehicle to implement augmented reality. One or more of an autonomous driving vehicle, a user terminal, and a server of the present invention can be linked to an artificial intelligence module, a drone (unmanned aerial vehicle, UAV), a robot, an augmented reality (AR) device, a virtual reality (VR) device, a device related to 5G services, etc.

Abstract: Systems and methods for verifying a detachment of a security tag from an article. The methods comprise: using a voltage induced in an internal circuit of the security tag by a magnetic field generated by a detaching unit to power a controller of the security tag; receiving, by the security tag, a first signal sent from the detaching unit; selectively supplying power to an electro-mechanical lock mechanism of the security tag for a certain amount of time to cause a pin to be released from a lock, in response to the first signal; and communicating, from the security tag, a second signal indicating whether or not the pin was released. The voltage is no longer induced in the internal circuit by the detaching unit when the second signal indicates that the pin was released.

Abstract: An adhesive film includes a porous metal layer having a plurality of pores therein, a first adhesive layer on one side of the porous metal layer, an adhesive substance at least partially filling the pores of the porous metal layer, and a plurality of first thermal conductive members distributed in the first adhesive layer.

Abstract: An electronic device is provided. The electronic device includes a first conductive patch, a second conductive patch, a third conductive patch, and a wireless communication circuit. The first conductive patch includes a first edge facing the second conductive patch, a second edge perpendicularly meeting the first edge at a first corner, a third edge parallel to the first edge, and a fourth edge that is parallel to the second edge and perpendicularly meets the third edge at a second corner. The second conductive patch and the third conductive patch each have a shape identical to that of the first conductive patch. The wireless communication circuit feed power to a first point of the first edge, a second point of a fifth edge of the second conductive patch, and a third point of a sixth edge of the third conductive patch.

Abstract: A semiconductor device is provided. The semiconductor device includes a metal layer, a semiconductor layer in electrical contact with the metal layer, a two-dimensional (2D) material layer disposed between the metal layer and the semiconductor layer and having a 2D crystal structure, and a metal compound layer disposed between the 2D material layer and the semiconductor layer.

Abstract: A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.

Abstract: An operating method of a nonvolatile memory device for programming multi-page data, the operating method including: receiving the multi-page data from a memory controller; programming first page data among the multi-page data to first memory cells connected to a word line adjacent to a selected word line; reading previous page data previously stored in second memory cells connected to the selected word line based on a first sensing value and a second sensing value after programming the first page data; calculating a first fail bit number by comparing first bits of the previous page data read based on the first sensing value to second bits of the previous page data read based on the second sensing value; and programming the previous page data read from the second memory cells and second page data among the multi-page data to the second memory cells based on the first fail bit number.

Abstract: A semiconductor device includes a substrate including a boundary region between first and second regions, first active patterns on the first region, second active patterns on the second region, and an isolation insulating pattern on the boundary region between the first and second active patterns. A width of at least some of the first active patterns have different widths. Widths of the second active patterns may be equal to each other. A bottom surface of the isolation insulating pattern includes a first bottom surface adjacent to a corresponding first active pattern, a second bottom surface adjacent to a corresponding second active pattern, and a third bottom surface between the first bottom surface and the second bottom surface. The third bottom surface is located at a different height from those of the first and second bottom surfaces with respect to a bottom surface of the substrate.

Abstract: A variable resistance memory device includes a first conductive line extending on a substrate in a first horizontal direction; a second conductive line extending on the first conductive line in a second horizontal direction perpendicular to the first horizontal direction; and a memory cell at an intersection between the first conductive line and the second conductive line, the memory cell including a selection element and a variable resistor, wherein the variable resistor includes a first variable resistance layer having a senary component represented by CaGebSbcTedAeXf, in which A and X are each a group 13 element different from each other, and 1?a?18, 13?b?26, 15?c?30, 35?d?55, 0.1?e?8, 0.1?f?8, and a+b+c+d+e+f=100.

Abstract: A method for distributed processing of an artificial intelligence model includes: obtaining an artificial intelligence model to be distributed and processed, dividing the artificial intelligence model to obtain a plurality of submodels processable in parallel, determining a first processing device to process a first submodel requiring a greatest amount of computations from among the plurality of submodels, predicting a first processing time required for the first processing device to process the first submodel, determining a second processing device to process a second submodel from among the plurality of submodels based on the predicted first processing time, and performing the distributed processing of the artificial intelligence model by requesting the first processing device and the second processing device to process the first submodel and the second submodel, respectively.

Abstract: A semiconductor device including a substrate; gate structures spaced apart from each other on the substrate, each gate structure including a gate electrode and a gate capping pattern; source/drain patterns on opposite sides of the gate structures; first isolation patterns that respectively penetrate adjacent gate structures; and a second isolation pattern that extends between adjacent source/drain patterns, and penetrates at least one gate structure, wherein each first isolation pattern separates the gate structures such that the gate structures are spaced apart from each other, the first isolation patterns are aligned with each other, and top surfaces of the first and second isolation patterns are each located at a level the same as or higher than a level of a top surface of the gate capping pattern.

Abstract: Provided is a distance measurement system, including: at least one sound source configured to generate an acoustic signal; an acoustic sensor including a plurality of directional acoustic sensors arranged to have directionalities different from one another; and at least one processor configured to: obtain a directionality of the acoustic signal in a particular direction based on at least one of a sum of output signals of the plurality of directional acoustic sensors or a difference between the output signals of the plurality of directional acoustic sensors, the at least one of the sum or the difference being based on applying a weight to at least one of the output signals; and determine a distance between the acoustic sensor and a reflection surface based on a time for the acoustic signal to arrive at the acoustic sensor in the particular direction after being generated and then reflected from the reflection surface.

Abstract: Disclosed is a memory device which includes a memory core that includes a plurality of memory cells, and control logic that receives a first active command and a first row address from an external device and activates memory cells corresponding to the first row address from among the plurality of memory cells in response to the first active command. The control logic includes registers and counters. The control logic records the first row address in one of the registers, counts an activation count of the first row address by using a first counter of the counters, and counts a lifetime count of the first row address by using a second counter of the counters.

Abstract: A semiconductor package includes a semiconductor chip, a redistribution insulating layer having a first opening, and an external connection bump including a first portion filling the first opening. A lower bump pad includes a first surface and a second surface opposite the first surface. The first surface includes a contact portion that directly contacts the first portion of the external connection bump and a cover portion surrounding side surfaces of the contact portion. A first conductive barrier layer surrounds side surfaces of the lower bump pad and is disposed between the lower bump pad and the redistribution insulating layer. A redistribution pattern directly contacts the second surface of the lower bump pad and is configured to electrically connect the lower bump pad to the semiconductor chip.

Abstract: Provided are a method for performing wireless communication by a first device, and an apparatus for supporting same. The method may comprise the steps of: establishing a first session for SL communication with a second device; transmitting auxiliary information relating to the SL communication to a base station; and receiving information on a resource relating to the SL communication from the base station.

Abstract: A display transferring structure includes a transfer substrate including a plurality of recesses, each of the plurality of recesses including a first trap having a space in which a predetermined object can be moved and a second trap connected to the first trap and having a shape and size in which the object can be seated; and a micro-semiconductor chip positioned in the second trap. The micro-semiconductor chip may be self-aligned in a correct position by the display transferring structure.

Abstract: An electric apparatus and a control method thereof. The electronic apparatus including a housing; a first door rotationally arranged on one side of the housing; a second door rotationally arranged on the other side of the housing; a first motor operationally connected to the first door; a second motor operationally connected to the second door; a first motor driver electrically connected to the first motor; a second motor driver electrically connected to the second motor; and a processor electrically connected to the first motor driver and the second motor driver, wherein the processor may control the first motor driver to drive the first motor to close the first door at a time different than a time the second door that is connected to the second motor driven by the second motor driver closes.

Abstract: Provided are a display panel and a display device, where the display panel includes a first light-emitting unit and a first color-resist block which are correspondingly disposed, where the first color-resist block includes a first display color-resist block and a first imaging color-resist block, the first light-emitting unit includes a first boundary and a second boundary which are disposed opposite to each other, the first boundary is located on a side of the second boundary near the first imaging color-resist block, the first display color-resist block includes a first edge and a second edge which are disposed opposite to each other, the first edge is located on a side of the second edge near the first imaging color-resist block, and a maximum distance between the first boundary and the first edge is greater than a maximum distance between the second boundary and the second edge.

Abstract: An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include a temperature sensor circuit and core circuitry. The temperature senor circuit may include at least one portion formed in a region other than the region that the IGFETs are formed as well as at least another portion formed in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming a portion of the temperature sensor circuit in regions below the IGFETs, an older process technology may be used and device size may be decreased and cost may be reduced.