Abstract: An independent hardware pixel counter counts bits of print data in regions of interest. The independent pixel counter can be an application specific integrated circuit (ASIC), and is separate from a control processor. The independent hardware pixel counter selectively monitors a data bus carrying image data to or from a memory. Once the pixels of the image data have been counted, the count data can be sent to the control processor in order to implement a print strategy. The pixel counter counts the print data at a point when image data is being sent to the memory, since at that point the image data is both uncompressed and in a raster format, and thus can be easily analyzed. Additionally, because the image data is stored in the memory until enough print data has accumulated for printing, the processor is provided with sufficient time to gather and use print information before the counted image data is printed.

Abstract: The invention relates to an inkjet temperature regulation controller that includes a time base circuit adapted to generate a clock signal and a head temperature sampler adapted to generate head temperature data by sensing print head temperature responsive to the clock signal. A preheat data generating circuit is adapted to translate the head temperature data into head preheat temperature data. A preheat data delivering circuit is adapted to provide the preheat temperature data to at least one preheating element. A monitor circuit is adapted to generate statistical data according to the head temperature data. The preheat data generating circuit receives updated head preheat temperature data responsive to the statistical data.

Abstract: A pulse width position modulator (PWPM) includes a digital delay circuit that outputs multiple subclocks according to a native pixel clock. The multiple subclocks are each skewed within different time periods of the native pixel clock period. A skew pulse generator receives the multiple subclocks from the digital delay circuit and outputs multiple subpixels according to different logical combinations of the multiple subclocks thereby providing increased subpixel output resolution using the native pixel clock. A clock skew synchronizer aligns the subpixels with a line synchronization signal. The clock skew synchronizer allows lines in a printed image to be aligned with the line synchronization signal within subpixel resolution without using high frequency sampling circuity.

Abstract: A Universal Serial Bus (USB) peripheral bridge and method for operation are disclosed. The bridge simulates a device disconnect condition to its upstream USB hub or host, even though it remains connected and powered, when its associated peripheral is not ready to communicate, powered off, or physically disconnected. For an IEEE-1284-1994 peripheral connection, the bridge senses the condition of the PLH peripheral line. If the PLH line is deasserted or floating, the bridge simulates a device disconnect condition by either allowing its upstream hub or host to take the D+ data line low, or taking the line low itself. By not allowing itself to be enumerated on the USB unless its associated peripheral is ready, the bridge avoids confusion at the host and wasted bus resources. At the same time, the bridge may remain physically connected to the host regardless of the state of the peripheral, even if the bridge is powered from the host.

Abstract: The current augmentation method is for use with a computer powered peripheral subsystem including a dynamic load, the dynamic load requiring greater power, from time to time, than the specified power available from the computer and specified interconnect bus or interface. This method includes use of a power node supplying power as necessary from the battery to the dynamic load, such that the varying dynamic load does not exceed the specified power available from the computer and interconnect bus. The method includes monitoring the load current, and injecting current into the power node to augment the current drive capability of the computer and peripheral bus. Preferably, the injecting is performed selectively based upon the result of the monitoring, e.g. only when the sensed load current is approaching a defined threshold level. Further, battery charging is performed only when it is determined that no current is being drawn through the battery to avoid distorting the voltage reading.

Abstract: A hybrid bilinear scaling (Qscale) scheme produces output images that have comparable quality to traditional bilinear interpolation algorithms, but requires a less complex hardware implementation. The Qscale system does not reverse-map output pixels back to arbitrary locations in the input space as defined by the mapping function. Rather all pixel values and locations are calculated after all of the original input pixels are mapped to the output. That is, all of the original image pixels are used “as-is” in the resultant scaled image. New pixels are generated from the original input pixels to meet the desired output pixel dimensions. Because only new pixels are computed, the Qscale system is less computationally complex. The computational requirements are further reduced because new pixels are computed between original pixel pairs meaning only two pixels are involved in the computation. Coefficients can be chosen to be fractional powers of two (0.5, 0.25, 0.

Abstract: A Universal Serial Bus to parallel bus bridge includes a Universal Serial Bus port that receives a serial bit stream of data and commands in a Universal Serial Bus protocol from a USB host computer. A parallel bus port on the bridge includes parallel port registers and state machines coupled to a peripheral device. A USB controller core is coupled between the Universal Serial Bus port and the parallel bus port and converts data and commands between the Universal Serial Bus protocol and the parallel bus protocol. A sequencer is coupled between the USB controller core and the parallel bus port. A sequence of sequencer commands is loaded into memory in the USB bridge and used by the sequencer to perform a sequence of parallel port operations. The sequencer performs the commands autonomously without intervention from the USB host computer.

Abstract: A serial to parallel port signal converter for interconnection between a hosts utilizing Uniform Serial Bus communications protocols and a peripheral device uses IEEE 1284 complaint communications protocol. The signal converter appears to the host as a fully compliant bi-directional USB device, and to the peripheral device as a fully compliant IEEE 1284 host.

Abstract: A serial to parallel port signal converter for interconnection between a hosts utilizing Uniform Serial Bus communications protocols and a peripheral device uses IEEE 1284 complaint communications protocol. The signal converter appears to the host as a fully compliant bi-directional USB device, and to the peripheral device as a fully compliant IEEE 1284 host.