Abstract: A user customizable integrated circuit architecture having separate regions for different types of core cells. In an embodiment of the present invention, all asynchronous core cells are placed in a first region and all synchronous core cells are placed in a second region thus allowing clock circuitry to be shared and clock traces to be efficiently routed. Clock buffers may also be placed in the second region. In a second embodiment, high-drive buffers are placed in the second region to enable efficient routing of high-drive power traces to the synchronous cells. Each region also may include metal programmable core cells that may be customized by the user for each design.

Abstract: A layout architecture for routing local and global interconnections for a gate array integrated circuit wherein basic cells are arranged as an array with columns and rows. Local interconnection and global interconnections are routed on the first metal layer in a direction parallel to the rows (horizontal). Power supply signals and global interconnection are routed in the second metal layer in a direction parallel to the rows (horizontal). Global interconnections are routed on the third metal layer in a direction parallel to the columns (vertical).

Abstract: A CMOS cell architecture and routing technique is optimized for three or more interconnect layer cell based integrated circuits such as gate arrays. First and second layer interconnect lines are disposed in parallel and are used as both global interconnect lines and interconnect lines internal to the cells. Third layer interconnect lines extend transverse to the first two layer interconnects and can freely cross over the cells. Non-rectangular diffusion regions, shared gate electrodes, judicious placement of substrate contact regions, and the provision for an additional small transistor for specific applications are among numerous novel layout techniques that yield various embodiments for a highly compact and flexible cell architecture. The overall result is significant reduction in the size of the basic cell, lower power dissipation, reduced wire trace impedances, and reduced noise.

Abstract: A gate array basic cell and circuit layout architecture for efficiently routing power supply traces. A basic cell has one or more transistors PMOS and one or more NMOS formed by diffusion regions and gate regions. A portion of the diffusion region extends outward to a point past the end of the gate region. Basic cells are arranged in rows with each basic cell having its p-type diffusion region extending in a direction opposite the n-type diffusion region. Basic cells are arranged in rows. Power supply traces are placed between rows, across the extended diffusion regions. Adjacent rows are shifted with respect to each other. A power supply trace is shared by adjacent rows of basic cells such that a connection can be made between the power supply trace and the extended diffusion regions without additional routing.