Patents Assigned to Industry-Academic Cooperation Foundation Yonsei University
  • Publication number: 20220150453
    Abstract: An apparatus for acquiring images includes an image sensor and a signal processor. The image sensor may include a sensor substrate and a color separation lens array, wherein the sensor substrate includes a plurality of photo-sensing cells, and the color separation lens array may separate an incident light into a plurality of lights having different wavelengths and forms a phase distribution for condensing the plurality of lights having the different wavelengths on adjacent photo-sensing cells of the plurality of photo-sensing cells. The signal processor may perform deconvolution on sensing signals of the plurality of photo-sensing cells to obtain a sub-sampled image, perform demosaicing to restore a full resolution image having a full resolution from the sub-sampled image, and correct a color of the full resolution image using a point spread function (PSF) of the color separation lens array.
    Type: Application
    Filed: November 3, 2021
    Publication date: May 12, 2022
    Applicants: SAMSUNG ELECTRONICS CO., LTD., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Sangyun LEE, Moongi KANG, Seokho YUN, Jonghyun KIM, Kyeonghoon JEONG
  • Publication number: 20220148644
    Abstract: An integrated circuit includes: a cell array including a plurality of memory cells in a plurality of first rows and a plurality of write assistance cells in at least one second row; a plurality of word lines respectively extending on the plurality of first rows; at least one write assistance line respectively extending on the at least one second row; and a row driver connected to the plurality of word lines and the at least one write assistance line, the row driver being configured to, during a write operation, activate at least one of the plurality of write assistance cells through the at least one write assistance line, wherein each of the plurality of write assistance cells includes the same transistor configuration as each of the plurality of memory cells and has the same footprint as each of the plurality of memory cells.
    Type: Application
    Filed: June 1, 2021
    Publication date: May 12, 2022
    Applicant: Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Heekyung Choi, Taemin Choi, Seongook Jung, Keonhee Cho
  • Patent number: 11326247
    Abstract: Provided is a transparent structure having improved wear resistance and flexibility, and a structure according to the present invention is a nanolayered structure in which a nitride nanofilm of one or more elements selected from metals and metalloids; and a boron nitride nanofilm are alternately layered.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: May 10, 2022
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Dae-Eun Kim, Oleksiy Penkov, Kuk Jin Seo
  • Patent number: 11330444
    Abstract: Disclosed is a control device for determining cognitive radio terminals. The device comprises: a spectrum sensing information storage unit for receiving and storing interference amount information for each frequency from spectrum sensing devices; a communication success probability calculation unit for receiving position information from secondary user terminals within a network and calculating a communication success probability of each secondary user terminal; a reinforced learning unit for setting the communication success probability as an initial access probability for each of the secondary user terminals and enabling learning such that an access probability, a state function, and a utility function are updated for each of the secondary user terminals at each iteration; and a cognitive radio terminal determining unit for, when the leaning is completed in the reinforced learning unit, selecting a secondary user terminal to execute cognitive radio communication on the basis of a final access probability.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 10, 2022
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Seong-Lyun Kim, Han Cha, Jee Min Kim
  • Publication number: 20220138563
    Abstract: A method and a device with deep learning operations. An electronic device includes a processor configured to simultaneously perform, using a systolic array, a plurality of tasks, wherein the processor includes the systolic array having a plurality of processing elements (PEs), and a first on-chip network that performs data propagation between two or more of the plurality of PEs, where each of the plurality of tasks includes one or more deep learning operations.
    Type: Application
    Filed: June 3, 2021
    Publication date: May 5, 2022
    Applicants: Samsung Electronics Co., Ltd., Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Hyung-Dal KWON, Youngsok KIM, Jounghoo LEE, Jin Woo CHOI
  • Patent number: 11321556
    Abstract: The present disclosure can provide a person re-identification apparatus and method that includes an identity feature extraction part configured to receive a multiple number of images each including a person requiring re-identification, extract features related to an identity of a person included in each image according to a pattern estimation method learned beforehand, and obtain an identity-related feature vector for each image; and a re-identification determination part configured to analyze a degree of similarity between an identity-related feature vector obtained for a base image including a search target from among the plurality of images and an identity-related feature vector obtained for another image to determine whether or not a person corresponding to the search target is included in the other image.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: May 3, 2022
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Bum Sub Ham, Chan Ho Eom
  • Publication number: 20220130667
    Abstract: A method of manufacturing a stacked structure includes forming a first metal buffer layer including crystal grains on a base substrate, forming a second metal buffer material layer on the first metal buffer layer, and crystallizing the second metal buffer material layer to form a second metal buffer layer, wherein the second metal buffer material layer includes crystal grains, and a density of the crystal grains of the second metal buffer material layer is lower than a density of the crystal grains of the first metal buffer layer.
    Type: Application
    Filed: September 8, 2021
    Publication date: April 28, 2022
    Applicants: Samsung Display Co., LTD., Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Mann Ho CHO, Kwang Sik JEONG, Hyeon Sik KIM, Hyun Eok SHIN, Byung Soo SO, Ju Hyun LEE
  • Publication number: 20220130453
    Abstract: An integrated circuit memory device includes a static random access memory (SRAM) cell, and a charge storing circuit electrically coupled to the SRAM cell. A switching controller is provided, which is electrically coupled to the charge storing circuit. The switching controller and the charge storing circuit are collectively configured to save power by recycling charge associated with a bit line electrically coupled to the SRAM cell by: (i) transferring charge from the bit line to a charge storage node electrically coupled to source terminals of a pair of NMOS pull-down transistors within the SRAM cell upon commencement of a SRAM cell write operation, and then (ii) returning at least a portion of the charge to the bit line upon completion of the SRAM cell write operation.
    Type: Application
    Filed: May 27, 2021
    Publication date: April 28, 2022
    Applicants: Samsung Electronics Co., Ltd., Industry Academic Cooperation Foundation, Yonsei University
    Inventors: Taemin Choi, Seongook Jung, Keonhee Cho
  • Patent number: 11315657
    Abstract: The present embodiments provide a stacked memory apparatus and a repairing method thereof which store information about a spare resource in a pre-bond process, check a spare resource available in a post-bond process, correct an error through an error correction code, and variably use the same number of spare resources to additionally ensure a number of spare resources in the post-bond process, thereby improving a yield.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: April 26, 2022
    Assignee: Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Sungho Kang, Dong Hyun Han, Ha Young Lee
  • Publication number: 20220123263
    Abstract: An organic light emitting display device may include a filling part filling a space between a second substrate and an organic light emitting diode, and a dam structure disposed in a non-display area and surrounding the filling part. At least one of the dam structure and the filling part includes a getter. The getter of the present disclosure is composed of magnesium oxide particles whose surfaces are modified into a first surface modification part made of an amino silane-based compound and a second surface modification part bound to the first surface modification part and made of a compound containing an acrylate group and a methacrylate group. Accordingly, it is possible to provide an organic light emitting display device that has high transparency and of which optical properties and durability are improved by minimizing permeation of water and oxygen.
    Type: Application
    Filed: October 5, 2021
    Publication date: April 21, 2022
    Applicants: LG DISPLAY CO., LTD., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Jaebin SONG, Dawoon JEONG, SungHee KIM, Suyeon LEE, JaeMin MYOUNG, Sung-Doo BAEK, MinSeong Kim
  • Patent number: 11309437
    Abstract: Provided are a vertical Schottky barrier diode using a two-dimensional layered semiconductor and a fabrication method thereof, the vertical Schottky barrier diode having excellent response characteristics in a high frequency region and capable of being directly fabricated from a material having a low melting point such as glass or plastic because its fabrication process is performed at a relatively low temperature. The vertical Schottky barrier diode includes: an ohmic contact layer formed of a metal; a two-dimensional layered semiconductor formed of two-dimensional transition metal dichalcogenides (TMDs) on one surface of the ohmic contact layer; a Schottky contact layer formed on one surface of the two-dimensional layered semiconductor; and a non-conductive layer formed on the other surface of the ohmic contact layer or one surface of the Schottky contact layer.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: April 19, 2022
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Seongil Im, Sung Jin Yang
  • Publication number: 20220112515
    Abstract: Disclosed herein are methods for producing virus-infected cell lines or animal models, wherein an enveloped virus including a lipid bilayer is mixed with a bile acid or a bile acid derivative, which allows the lipid bilayer to be replaced with a lipid bilayer derived from a target animal. Also disclosed herein are the virus-infected cell lines or animal models so produced and methods of screening a therapeutic candidate for a viral disease using the same.
    Type: Application
    Filed: October 25, 2019
    Publication date: April 14, 2022
    Applicants: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY, UNIVERSITY INDUSTRY FOUNDATION, YONSEI UNIVERSITY WONJU CAMPUS
    Inventors: Hong Jai Lee, Soo Ki Kim, Jae Seung Moon, Bo Young Shin, Jin Su Shin, Sang Kyou Lee
  • Publication number: 20220115060
    Abstract: A memory device accessed by circuits operating based on a first supply voltage. The memory device includes a cell array electrically connected to a plurality of word lines and a plurality of bit lines; a row driver configured to select one word line of the plurality of word lines based on a row address; a precharge circuit configured to precharge the plurality of bit lines based on the first supply voltage; a column driver configured to select at least one bit line of the plurality of bit lines based on a column address; and a read circuit configured to read data stored in the cell array through the at least one bit line. The cell array, the row driver, the column driver, and the read circuit operate based on a second supply voltage, which is higher than the first supply voltage.
    Type: Application
    Filed: September 17, 2021
    Publication date: April 14, 2022
    Applicants: Samsung Electronics Co., Ltd., Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Taemin Choi, Taehyun Kim, Seongook Jung
  • Patent number: 11301970
    Abstract: An image processing method acquires an image, restores a saturated region in which a pixel in the image has a first reference value based on a first illuminance component of the image, enhances a dark region in which a value of a pixel in the image is less than a second reference value based on the restored saturated region and the first illuminance component, and outputs a dark region-enhanced image.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: April 12, 2022
    Assignees: Samsung Electronics Co., Ltd., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Hwiryong Jung, Moon Gi Kang, Seung Hoon Jee, Min Sub Kim, Wooshik Kim, Hyewon Moon, Keechang Lee, Sunghoon Hong
  • Patent number: 11301371
    Abstract: An electronic device is provided. A memory controller, having an improved response time for an input/output request and increased capacity of Dynamic Random Access Memory (DRAM) according to the present disclosure, includes an available-time prediction component configured to perform a machine learning operation using a Recurrent Neural Network (RNN) model based on input/output request information about an input/output request input from a host, and to predict an idle time representing a time during which the input/output request is not expected to be input from the host and a data compression controller configured to generate, in response to the idle time longer than a set reference time, compressed map data by compressing map data which indicates a mapping relationship between a logical address provided by the host and a physical address indicating a physical location of a memory block included in the memory device.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: April 12, 2022
    Assignees: SK hynix Inc., Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Junhyeok Jang, Myoungsoo Jung
  • Patent number: 11281381
    Abstract: Provided herein is a storage node of a distributed storage system and a method of operating the same. A memory controller may include a data controller configured to receive a write request and write data corresponding to the write request from a host, and configured to determine a physical address of a memory block in which the write data is to be stored based on chunk type information included in the write request, a memory control component configured to provide a program command for instructing the memory block to store the write data, the physical address, and the write data to the memory device, wherein the chunk type information is information about whether the write data indicates a type of data chunks or a type of coding chunks, the data chunks and the coding chunks being generated by the host performing an erasure coding operation on original data.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: March 22, 2022
    Assignees: SK hynix Inc., Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Sungjoon Koh, Myoungsoo Jung
  • Publication number: 20220083515
    Abstract: A storage system includes a storage device having a nonvolatile memory with a first and a second physical address and a host configured to insert a first journal logical address and a first target logical address into a journal mapping table. The storage device includes a flash mapping table storing the first journal logical address mapped to the first physical address, and the first target logical address mapped to the second physical address; a circuit configured to write the first journal data to an area of the nonvolatile memory to the first physical address corresponding to the first journal logical address according to the first mapping state, based on the journaling command; and to change the first mapping state of the flash mapping table to a second mapping state in which the first target logical address is remapped to the first physical address, based on the checkpointing command.
    Type: Application
    Filed: June 8, 2021
    Publication date: March 17, 2022
    Applicants: Samsung Electronics Co., Ltd., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Joo Hyeong YOON, Won Woo RO, Won Seb JEONG
  • Publication number: 20220081742
    Abstract: There are a composite material including an aluminum-based matrix and a device adopting the same. The composite material including an aluminum-based matrix may include an aluminum-based matrix including a plurality of grains, wherein each of the grains has a plurality of sub-grains; and a self-organized phase present at a sub-grain boundary between the plurality of sub-grains, wherein the self-organized phase has a band structure and includes a solid solution of aluminum and a non-metal element. The sub-grains and the self-organized phase coming into contact with the sub-grains may form a substantially coherent interface. A plurality of dislocations spaced apart from each other may be provided along the coherent interface.
    Type: Application
    Filed: September 10, 2021
    Publication date: March 17, 2022
    Applicant: Industry-Academic Cooperation Foundation, Yonsei University
    Inventor: Dong Hyun BAE
  • Patent number: 11276452
    Abstract: A memory system includes a memory device including a first area being refreshed according to a first refresh period and a second area begin refreshed according to a second refresh period longer than the first refresh period. The memory system also includes a memory controller configured to generate a write command and a write data corresponding to a first write request and a first data.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: March 15, 2022
    Assignees: SK hynix Inc., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Won Woo Ro, Hyunwuk Lee, Gun Ko, Ipoom Jeong, Min Seong Kim, Yong Tag Song, Sung Jae Lee
  • Patent number: 11274074
    Abstract: The present disclosure relates to a novel anticancer pharmaceutical composition. The present disclosure achieves an anticancer effect using a compound effective in inhibiting the expression of ANO1 (TMEM16A). In addition, the present disclosure provides an ANO1 (TMEM16A) antagonist using the compound inhibiting the expression of ANO1 (TMEM16A).
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: March 15, 2022
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION YONSEI UNIVERSITY
    Inventors: Wan Namkung, Ik Yon Kim, Yohan Seo, Jin Hwang Kim