Abstract: In one implementation, an optimized multi-root input-output virtualization (MRIOV) aware switch configured to route data between multiple root complexes and I/O devices is described. The MRIOV aware switch may include two or more upstream ports and one or more downstream ports. Each of an upstream port and a downstream port may include a media access controller (MAC) configured to negotiate link width and link speed for exchange of data packets between the multiple root complexes and the I/O devices. Each of an upstream port and a downstream port may further include a clocking module configured to dynamically configure a clock rate of processing data packets based one or more negotiated link width and negotiated link speed, and a data link layer (DLL) coupled to the MAC configured to operate at the clock rate, wherein the clock rate is indicative of processing speed.

Abstract: Described herein are methods and system for virtualization of the secure digital (SD) host controller to enable sharing a SD device among various multiple host processors in a multi-processor computing system. In one implementation the method of sharing a SD device amongst a plurality of hosts of a multi-host computing system comprises detecting the SD device on occurrence of a reset event, receiving an enumeration request, from at least a first host and a second host of the plurality of hosts, to enumerate the SD device with respect to the second host, enumerating the SD device with respect to the second host, and initiating data exchange between the SD device and each of the plurality of hosts.

Abstract: Described herein is a detachable multi-host computing system (100) having multiple host processors running different operating systems. In one implementation, the multi-host computing system (100) includes a detachable unit (102) and a base unit (104). Each of the detachable unit (102) and the base unit (104) includes an MR-IOV switch and a MR-PCIM for controlling the MR-IOV switch. In one embodiment, the MR-PCIM for both the detachable unit (102) and the base unit (104) is configured such that a single MR-PCIM switch may be used for enumerating peripheral devices connected to the detachable unit (102) and the base unit (104) when the detachable unit (102) and the base unit (104) are in an attached mode.

Abstract: Described herein are methods and systems for virtualization of a USB device to enable sharing of the USB device among a plurality of host processors in a multi-processor computing system. A USB virtualization unit for sharing of the USB device include a per-host register unit, each corresponding to a host processor includes one or more of a host register interface, host data interface, configuration registers, and host control registers, configured to receive simultaneous requests from one or more host processors from amongst the plurality of host processors for the USB device. The USB virtualization unit also includes a pre-fetch direct memory access (DMA) configured to pre-fetch DMA descriptors associated with the requests to store in a buffer. The USB virtualization unit further includes an endpoint specific switching decision logic (ESL) configured to schedule data access based on the DMA descriptors from the host processor's local memory corresponding to each request.

Abstract: Described herein is a system having a multi-host low pin count (LPC) controller (100) configured to facilitate sharing of common peripheral devices by multiple hosts (115) of a multi-host computing system (110). In one implementation, the multi-host LPC controller (100) interfaces with the hosts (115) via an ON-chip bus or an LPC-IN-chip bus. Further, the multi-host LPC controller (100) includes a LPC-IN controller (160) and a microcontroller (155) to moderate among requests generated by the hosts (115). The requests can be target accesses, DMA accesses, and BM accesses. Also, the multi-host LPC controller (100) is configured to operate in a software mode and an auto mode. Based on the mode the multi-host LPC controller (100) is operating in, the requests generated by the various hosts are moderated.

Abstract: File system sharing in multi-host computing system (100) running multiple operating systems is described herein. A file systems stored on different data partitions (110-1) and (110-1), of different operating systems (106-1) and (106-2), running on a multi-host computing system (100) may be shared based on file server-client architecture. According to the implementation, an operating system (106-1) may share its file system as file server and other operating system (106-2) may access the shared file system as file client. In one implementation, the sharing of data between multiple hosts is enabled by a dedicated high speed, low latency. inter processor communication bus, FiRE (124).

Abstract: The present subject matter discloses methods and systems of application sharing in multi-host computing system (100) running multiple operating systems. In one embodiment, the method for application sharing in a multi-host computing system (100) comprises receiving a request to launch an application in a first operating system of the multi-host computing system (100) from a second operating system of the multi-host computing system (100), generating an application launch request to launch the application and transmitting the application launch request to a widget daemon running on the first operating system using a PCIe to PCIe application redirection engine. The method further comprises initiating an application sharing session between the first operating system of the multi-host computing system (100) from the second operating system of the multi-host computing system (100).

Abstract: Described herein is a system having a multi-host SATA controller (102) configured to provide communication and control between two or more independent host processors (104) and a single SATA device (108). In one implementation, the multi-host SATA controller (102) includes the device switching layer (206), the device control layer (208), the link layer (210), and the physical layer (212). The device switching layer (206) allows the host processors (104) to issue commands concurrently rather than in sequential order. For this, the device switching layer (206) has independent set of host device registers (214) corresponding to each of the host processors (104). The device switching layer (206) also has independent DMA engines (216) to perform a command pre-fetching from respective host system memories (105). Further, a command switch engine (220) may arbitrate commands in case both the host processors (104) wish to access the SATA device (108) simultaneously.