Abstract: An apparatus for providing a jittered clock signal has a reverse-biased diode. The reversed-biased diode has a leakage current which decreases a reverse voltage on the diode, time-dependent on a shot-noise of the leakage current. The apparatus for providing a jittered clock signal further has a unit for periodically increasing the reverse voltage of the diode to a value, which is above a switching value and the apparatus has a unit for comparing the reverse voltage of the diode to the switching value and for outputting a jittered clock signal dependent on the comparison.

Abstract: A method of forming a magnetic stack and a structure for a magnetic stack of a resistive memory device. A crystallization inhibiting layer is formed over the free layer of a magnetic stack, improving thermal stability. The crystallization inhibiting layer comprises an amorphous material having a higher crystallization temperature than the crystallization temperature of the free layer material. The crystallization inhibiting layer inhibits the crystallization of the underlying free layer, providing improved thermal stability for the resistive memory device.

Abstract: A reference current distribution method and structure thereof for MRAM devices. An MRAM array includes current reference paths with substantially uniform length and resistance for all current paths flowing from the global reference current generator (GRCG) to a plurality of local current generators (LCGs), each LCG being coupled to at least one sub-array. The conductive wire segments that couple the LCGs to the GRCG are positioned such that all reference current path lengths from the GRCG to each LCG are substantially the same, ensuring that the resistance of all reference current paths is substantially the same and the amount of reference current provided by the GRCG to the LCGs is substantially the same. An advantage of an embodiment of present invention may be that the write margin is increased for the MRAM chip.

Abstract: The damage to edge sections which occurs during the patterning of a metal-oxide-containing layer can be compensated by the deposition of an annealing layer and a subsequent heat treatment step through which a material flow takes place from the annealing layer into the damaged edge sections. The metal-oxide-containing layer can form the dielectric of a storage capacitor of a DRAM memory cell.