Abstract: There is provided an apparatus for protection against over voltages and/or under voltages. The apparatus includes a pass transistor through which an input voltage is applied, the input voltage varying between a low voltage and a high voltage, and means for selectively varying the gate voltage of the pass transistor when the input voltage is transitioning from the low voltage to the high voltage or from the high voltage to the low voltage. The pass transistor may include an NMOS or a PMOS transistor.

Abstract: A method of using bank tag registers in a multi-bank memory device to avoid background operation collision is described. A memory controller includes a plurality of bank registers, each of which is associated with one of a plurality of memory banks, wherein a bank register is arranged to store information, a bank number, a bank status, and a bank counter for a particular bank. The memory controller further includes an adjustable bank comparator coupled to each bank register. The memory controller receives an incoming system address request, which includes a requested bank number. The requested bank number is used to configure the adjustable bank comparator with the particular bank operating characteristics, to locate the bank register, and to determine the bank status and the bank entry status of the requested memory bank. The requested memory bank is accessed when the bank entry status identifies the requested memory bank as open.

Abstract: The memory has a control unit, which, in order to generate a common reference potential on the two bit lines, turns on the first switching element and the selection transistors of the two reference memory cells and, after a specific time period, turns off the selection transistors, while the first switching element remains in the on state and compensates for a potential difference between the two bit lines.