Abstract: A method for forming a contact hole in a semiconductor device and related computer-readable storage medium are provided, the method and program steps of the medium including measuring a percentage of oxygen in an etching chamber, and controlling the percentage of oxygen in the etching chamber to enlarge a temporary inner diameter near a top of the contact hole.
Type:
Grant
Filed:
February 7, 2011
Date of Patent:
August 7, 2012
Assignees:
Infineon North, Samsung Electronics Co., Ltd., International Business Machines Corporation, Chartered Semiconductor Manufacturing Ltd., Infineon Technologies AG
Abstract: A method for generating an embedded resistor in a semiconductor device and related computer-readable storage medium are provided, the method and program steps of the medium including forming a shallow trench isolation (STI) region in a substrate; forming a pad oxide on the STI region and substrate; depositing a silicon layer on the pad oxide; forming a photo-resist mask on a portion of the silicon layer disposed substantially above the STI region.
Type:
Application
Filed:
February 3, 2009
Publication date:
August 5, 2010
Applicants:
Samsung Electronics Co., Ltd., International Business Machines Corporation, FREESCALE SEMICONDUCTOR, INFINEON NORTH
Inventors:
Choongryul Ryou, Seunghwan Lee, Jun Yuan, Victor Chan, Manfred Eller, Nam Sung Kim, Narasimhulu Kanike, Srikanth Balaji Samavedam
Abstract: An electronic device including: a semiconductor substrate having an array of gate conductors, each having a length and a width, comprised of dummy gate conductors and functional gate conductors extending in a widthwise direction, the gate conductors positioned substantially parallel to each other in the widthwise direction and periodically spaced apart a fixed distance in a direction substantially perpendicular to the widthwise direction.
Type:
Application
Filed:
June 26, 2003
Publication date:
January 13, 2005
Applicants:
INTERNATIONAL BUSINESS MACHINES CORPORATION, INFINEON NORTH AMERICA CORP
Abstract: A process for forming a DRAM in a silicon chip that includes N-MOSFETs of the memory cells in its central area and C-MOSFETs of the support circuitry in the peripheral area. By the inclusion of a masking oxide layer over the peripheral area during the formation of the memory cells, there are formed N-MOSFETs that use N-doped polycide gates and P-MOSFETs that use P-doped polycide gates. The sources and drains include self-aligned silicide contacts.
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