Patents Assigned to Infineon North America Corp.
  • GATE LENGTH PROXIMITY CORRECTED DEVICE
    Publication number: 20050009312
    Abstract: An electronic device including: a semiconductor substrate having an array of gate conductors, each having a length and a width, comprised of dummy gate conductors and functional gate conductors extending in a widthwise direction, the gate conductors positioned substantially parallel to each other in the widthwise direction and periodically spaced apart a fixed distance in a direction substantially perpendicular to the widthwise direction.
    Type: Application
    Filed: June 26, 2003
    Publication date: January 13, 2005
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, INFINEON NORTH AMERICA CORP
    Inventors: Shahid Butt, Wayne Ellis, John Gabric
  • High performance DRAM and method of manufacture
    Patent number: 6235574
    Abstract: A process for forming a DRAM in a silicon chip that includes N-MOSFETs of the memory cells in its central area and C-MOSFETs of the support circuitry in the peripheral area. By the inclusion of a masking oxide layer over the peripheral area during the formation of the memory cells, there are formed N-MOSFETs that use N-doped polycide gates and P-MOSFETs that use P-doped polycide gates. The sources and drains include self-aligned silicide contacts.
    Type: Grant
    Filed: May 10, 2000
    Date of Patent: May 22, 2001
    Assignee: Infineon North America Corp.
    Inventors: Dirk Többen, Johann Alsmeier