Patents Assigned to Infineon Technologies Flash Ltd.
  • Patent number: 6975536
    Abstract: Apparatus including a virtual ground array, which includes memory cells connected in rows and columns to word lines and bit lines, respectively. The virtual ground array includes at least one block of data, and peripheral circuitry adapted to simultaneously access a plurality of subsets of the at least one block of data stored in the memory cells along at least one word line. Methods for operating the virtual ground array in a mass storage device include simultaneously accessing a plurality of subsets of at least one block of data stored in the memory cells along at least one word line.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: December 13, 2005
    Assignees: Saifun Semiconductors Ltd., Infineon Technologies Flash Ltd.
    Inventors: Eduardo Maayan, Ran Dvir, Zeev Cohen
  • Patent number: 6826107
    Abstract: A flash memory card including a controller, at least one control pad, at least one memory, and a high voltage switch logic module in communication with the at least one control pad, the controller and the at least one memory, the high voltage switch logic module being adapted to selectively route voltage from the at least one control pad to one of the controller and the at least one memory. If the voltage input to the at least one control pad does not exceed a predefined level, then the voltage may be routed from the at least one control pad to the controller. If the voltage input to the at least one control pad exceeds the predefined level, then the voltage may be routed from the at least one control pad to the at least one memory.
    Type: Grant
    Filed: August 1, 2002
    Date of Patent: November 30, 2004
    Assignees: Saifun Semiconductors Ltd., Infineon Technologies Flash Ltd.
    Inventors: Ran Dvir, Zeev Cohen
  • Patent number: 6781897
    Abstract: A method for defect detection, comprising providing a memory cell array comprising memory cells connected to word lines and local bit lines, and global bit lines connected to the local bit lines, the global bit lines comprising at least two portions, one portion connected to a voltage source, and the other portion connected to a defect detector, the defect detector comprising logic circuit components for outputting a logic signal, and detecting a defect comprising at least one of a short circuit and an open circuit in at least one of the word lines, local bit lines and global bit lines by detecting a signal at the defect detector. Embodiments of apparatus for carrying out the methods of the invention are also disclosed.
    Type: Grant
    Filed: August 1, 2002
    Date of Patent: August 24, 2004
    Assignee: Infineon Technologies Flash Ltd.
    Inventors: Ran Dvir, Eduardo Maayan, Zeev Cohen