Abstract: A high speed zero phase restart for a multiphase clock for a PRML read/write channel design. The zero phase restart includes an input for receiving a plurality of clock pulse waves, each having substantially equal period and each being out of phase with respect to other clock pulse waves; an output including at least one output terminal corresponding to one of the clock pulse waves; and a zero phase circuit configured to sequentially couple the plurality of clock pulse waves to the corresponding output terminals.

Abstract: A view DAC feedback inside an analog front circuit for a partial response, maximum likelihood based read/write channel is disclosed. The view DAC feedback circuit may be configured to apply an analog signal associated with an operation level of the PRML based read/write channel to the analog front circuit of the read channel. The view DAC analog signal may be used to calibrate operating parameters for a continuous time filter component of the analog front circuit. The view DAC feedback circuit may be configured to add digitally-controlled noise to the PRML read/write channel to optimize performance of the channel in a low signal-to-noise (SNR) environment.

Abstract: A offset cancellation of charge pump based phase detector is disclosed. The methods and circuits disclosed cancel inherent with a phase detector and imbalanced charge pumps. The offset cancellation includes detecting the phase detector and the charge pump offset with a calibration signal and a reference voltage source, and applying a calibration current to cancel the phase detector and charge pump offset.

Abstract: A high-speed programmable synchronous counter is disclosed. The high speed counter includes a most-significant-bit counter synchronized with a least-significant bit counter. The least-significant-bit counter is programmed to an initial state and configured to decrement a state with each pulse of a clock wave. The least-significant-bit counter provides an output signal when the least-significant-bit counter has a zero-count state. The most-significant-bit counter decrements when the least-significant-bit counter has a zero-count state and provides an output signal when the least-significant-bit counter has a zero-count state. A counter output pulse is generated and the high-speed counter is reset to the initial state when both the least-significant bit counter and the most-significant bit counter have a zero-count state.

Abstract: A low voltage charge pump for a phase locked loop is disclosed. The low voltage charge pump provides linear control for a voltage at a loop filter. The charge pump is supplied by a power supply between 1.6 and 2.0V and is configured to provide linear charging and discharging of the loop filter to a potential between 150 mVolts to within 150 mVolts of the power supply voltage.

Abstract: A write output driver with internal programmable pull-up resistive devices is disclosed. The write output driver provides an integrated output driver circuit configurable to provide near end transmission line termination. The output driver is configured to provide transmission of a high-speed signal with increased frequencies over prior output drivers. The output impedance of the output driver is programmable and maintained substantially constant, despite ambient fluctuations. An internal bias signal generator is provided to control the impedance of the output driver.