Abstract: An improved Universal Serial Bus interface employing FIFO buffers (300, 800) for interfacing to an application bus and a microprocessor bus, in particular, an XBUS. The interface includes a plurality of transmit/receive channels (114) multiplexed to the application bus and the XBUS. Each transmit channel includes a transmit FIFO buffer (300), a transmit write buffer (308), a transmit push buffer (310), and three transmit state machines: a transmit write state machine (302), a transmit interrupt state machine (313), and a transmit push state machine (313). The transmit state machine (302) and the transmit FIFO (300) are clocked in the USB domain. The transmit write register (308) is clocked in the XBUS domain. Each receive channel includes a receive FIFO buffer (800), a receive state machine (802), and a receive register (806). The receive FIFO (800), the receive state machine (802), and the receive register (806) are all clocked in the USB domain.