Abstract: An amplifier circuit includes an RF transistor, a parallel resonator and a series resonator. The RF transistor has an input, an output and an intrinsic output capacitance. The parallel resonator is connected to the output of the RF transistor and includes a first inductive component connected in parallel with the intrinsic output capacitance of the RF transistor. The series resonator connects the output of the RF transistor to an output terminal and includes a second inductive component connected in series with a capacitive component. The series resonator is operable to compensate for a change in impedance of the parallel resonator over frequency.

Abstract: A method is provided for forming a metal semiconductor alloy that includes providing a deposition apparatus that includes a platinum source and a nickel source, wherein the platinum source is separate from the nickel source; positioning a substrate having a semiconductor surface in the deposition apparatus; forming a metal alloy on the semiconductor surface, wherein forming the metal alloy comprises a deposition stage in which the platinum source deposits platinum to the semiconductor surface at an initial rate at an initial period that is greater than a final rate at a final period of the deposition stage, and the nickel source deposits nickel to the semiconductor surface; and annealing the metal alloy to react the nickel and platinum with the semiconductor substrate to provide a nickel platinum semiconductor alloy.

Abstract: A method of oxidizing a substrate having area of about 30,000 mm2 or more. The surface is preferably comprised of silicon-containing materials, such as silicon, silicon germanium, silicon carbide, silicon nitride, and metal suicides. A mixture of oxygen-bearing gas and diluent gas normally non-reactive to oxygen, such as Ne, Ar, Kr, Xe, and/or Rn are ionized to create a plasma having an electron density of at least about 1e12 cm?3 and containing ambient electrons having an average temperature greater than about 1 eV. The substrate surface is oxidized with energetic particles, comprising primarily atomic oxygen, created in the plasma to form an oxide film of substantially uniform thickness. The oxidation of the substrate takes place at a temperature below about 700° C., e.g., between about room temperature, 20° C., and about 500° C.

Abstract: Described are integrated circuit chips that are capable of self-adjusting an internal voltage of the integrated circuit chip and methods for adjusting the internal voltage of an integrated circuit chip. The methods include comparing an internally generated voltage to an external target voltage.

Abstract: A method of fabricating a trench capacitor of a memory cell, includes providing a semiconductor substrate with a surface covered by a pad layer, forming a trench in the substrate, forming a first layer on the pad layer and on the surface of the trench, removing a portion of the first layer to form a residual first insulating layer, forming a first conductive layer on the residual first layer, removing a portion of the first conductive layer, removing a portion of the residual first layer, driving out charged elements from the first layer into the semiconductor substrate, to form a first doped substrate region, removing the first layer, forming a node nitride on the trench, forming a second conductive layer on the pad layer and on the trench, removing a portion of the second conductive layer to form a second doped substrate region in the trench.

Abstract: A method for forming a back-side contact for a vertical trench device includes grinding a back-side of a semiconductor substrate, milling a trench in the back-side of the semiconductor substrate, wherein a vertical trench fill is exposed, and depositing a conductive material, wherein the conductive material shorts the vertical trench fill to a buried plate. Grinding the back-side of the semiconductor substrate further includes grinding a dimple beneath a portion of the vertical trench device, wherein the trench is milled in the bottom portion of the dimple.

Abstract: A method for exposing a workpiece in a dual exposure step-and-repeat process starts by forming a design for a reticle mask. Deconstruct the design for the reticle mask by removing a set(s) of the features that are juxtaposed to form hollow polygonally-shaped clusters with a gap in the center. Form unexposed resist on the workpiece. Load the workpiece and the reticle mask into the stepper. Expose the workpiece through the reticle mask. Reposition the workpiece by a nanostep. Then expose the workpiece through the reticle mask after the repositioning. Test whether the plural exposure process is finished. If the result of the test is NO the process loops back to repeat some of the above steps. Otherwise the process has been completed. An overlay mark is produced by plural exposures of a single mark. A dead zone is provided surrounding an array region in which printing occurs subsequent to exposure in an original exposure.

Abstract: An interface circuit for coupling a data handling unit with a memory unit having control inputs, an address signal input, a data signal input, and a data signal output is described. The interface circuit comprises an address buffer having an input and an output, said input receiving an address signal from said data handling unit, a first multiplexer which couples said memory unit with either said output of said address buffer or with said address signal, a data buffer having an input and an output, said input receiving a data signal from said data handling unit and said output being coupled with said memory data input, a second multiplexer for selecting either said memory data signal output or said data buffer output, and a comparator for comparing said address signal with the signal from said address buffer output, generating a control signal which controls said second multiplexer.

Abstract: A method for forming a memory device having low bitline capacitance, comprising: providing a gate conductor stack structure on a silicon substrate, said gate stack structure having a gate oxide layer, a polysilicon layer, a silicide layer, and a top dielectric nitride layer; oxidizing sidewalls of said gate oxide stack; forming sidewall spacers on the sidewalls of said gate conductor stack, said sidewall spacers comprising a thin layer of nitride having a thickness ranging from about 50 to about 250 angstroms; overlaying the gate structure with a thin nitride liner having a thickness ranging from about 25 to about 150 angstroms; depositing an insulative oxide layer over the gate structure; polishing the insulative oxide layer down to the level of the nitride liner of the gate structure; patterning and etching the insulative oxide layer to expose said nitride liner; forming second sidewall spacers over said first sidewall spacers, said second sidewall spacers comprising an oxide layer having a thickness rangin