Abstract: According to an embodiment, a multiphase regulator includes a plurality of output phases each of which is operable to deliver a phase current through a separate inductor to a load connected to the output phases via the inductors and an output capacitor. A controller is operable to regulate a voltage delivered to the load by adjusting the phase currents delivered to the load by the output phases, monitor the phase currents delivered to the load by the output phases, test the output phases in a predetermined sequence, and determine if the phase currents respond in a predetermined way.

Abstract: A power electronic device includes an Insulated Metal Substrate Printed Circuit Board (IMS PCB) and a power semiconductor device package. The power semiconductor device package includes a lead frame configured to electrically and mechanically couple the power semiconductor device package to the IMS PCB. The lead frame has a rigid configuration and is made of a lead frame material having a first thermal expansion coefficient. The IMS PCB includes an insulated metal substrate made of a substrate material having a second thermal expansion coefficient within a range of 60% to 140% of the first thermal expansion coefficient.

Abstract: A semiconductor device includes a first trench and a second trench in a first main surface of a semiconductor substrate. Each of the first and second trenches includes first sections extending lengthwise in a first direction and a second section extending lengthwise in a second direction transvers to the first direction, the second section of the first trench being disposed opposite to the second section of the second trench. The semiconductor device further includes a semiconductor mesa separating the first and second trenches, and a source metal layer above the first main surface of the semiconductor substrate and electrically connected to source regions in the semiconductor mesa. Corresponding methods of manufacture are also described.

Abstract: An electronic module includes a first insulation layer, at least one carrier having a first main surface, a second main surface situated opposite the first main surface, and side surfaces connecting the first and second main surfaces to one another, at least one semiconductor chip arranged on the second main surface of the carrier, wherein the semiconductor chip has contact elements, and a second insulation layer, which is arranged on the carrier and the semiconductor chip.

Abstract: A semiconductor device includes an electrically conductive lead frame which includes a die pad and a plurality of electrically conductive leads, each of the leads in the plurality being spaced apart from the die pad. The semiconductor device further includes first and second integrated switching devices mounted on the die pad, each of the first and second integrated switching devices include electrically conductive gate, source and drain terminals. The source terminal of the first integrated switching device is disposed on a rear surface of the first integrated switching device that faces and electrically connects with the die pad. The drain terminal of the second integrated switching device is disposed on a rear surface of the second integrated switching device that faces and electrically connects with the die pad.

Abstract: Circuits and devices for bidirectional normally-off switches are described. A circuit for a bidirectional normally-off switch includes a depletion mode transistor and an enhancement mode transistor. The depletion mode transistor includes a first source/drain node, a second source/drain node, a first gate, and a second gate. The enhancement mode transistor includes a third source/drain node and a fourth source/drain node, and a third gate. The third source/drain node is coupled to the first source/drain node.

Abstract: In an embodiment, a DC-DC power conversion circuit with a step-down conversion ratio of at least 12:1 is provided. The DC-DC power conversion circuit includes a half-bridge circuit arrangement, a resonant capacitor and a module including a hybrid transformer. The hybrid transformer includes a magnetic core and a primary winding electrically coupled in series with a secondary winding. The module further includes a synchronous rectifier having an output coupled between the primary winding and the secondary winding of the hybrid transformer, and an output capacitor coupled with an output of the secondary winding.

Abstract: A MEMS device is provided. The MEMS device includes a membrane, and at least one electrode arranged at a distance from the membrane. The at least one electrode includes a layer stack. The layer stack includes a first insulation layer, a first conductive layer arranged thereabove, a second insulation layer arranged thereabove, a second conductive layer arranged thereabove, and a third insulation layer arranged thereabove.

Abstract: A semiconductor device includes needle-shaped trenches in a semiconductor substrate, each of which includes a field electrode electrically insulated from the semiconductor substrate. Source doping regions and body doping regions of a transistor arrangement are formed in the semiconductor substrate between neighboring ones of the needle-shaped trenches. Gate trenches extend through the source doping regions and the body doping regions. The device further includes a first insulation layer above the semiconductor substrate, an etch stop layer on the first insulation layer, a second insulation layer on the etch stop layer, and an electrically conductive material on the second insulation layer and which contacts the field electrodes, source doping regions and body doping regions through openings which extend through the second insulation layer, etch stop layer and first insulation layer.

Abstract: A method of forming a compound semiconductor substrate includes providing a crystalline base substrate having a first semiconductor material and a main surface, and forming a first semiconductor layer on the main surface and having a pair of tracks disposed on either side of active device regions. The first semiconductor layer is formed from a second semiconductor material having a different coefficient of thermal expansion than the first semiconductor material. The pair of tracks have a relatively weaker crystalline structure than the active device regions. The method further includes thermally cycling the base substrate and the first semiconductor layer such that the first semiconductor layer expands and contracts at a different rate than the base substrate. The pair of tracks physically decouple adjacent ones of the active device regions during the thermal cycling.

Abstract: Disclosed is a power converter circuit and a method for operating the power converter circuit. The power converter circuit includes at least one converter stage and a control circuit. The at least one converter stage includes an input configured to receive an input power, an output configured to supply an output power, a first electronic switch, and a first inductor coupled to the first electronic switch. The control circuit includes a hysteresis controller configured to drive the first electronic switch based on a current measurement signal representing a current through the inductor, a first threshold signal, and a second threshold signal, and an operating point controller configured to detect an operating point of the converter stage to generate the first threshold signal and the second threshold signal based on the detected operating point.

Abstract: According to an embodiment, a capacitance determination circuit is provided comprising a voltage controlled oscillator configured to generate a frequency signal whose frequency depends on a control voltage supplied to the voltage controlled oscillator, a capacitor coupled to the voltage controlled oscillator wherein the control voltage depends on a voltage across the capacitor and a processing circuit configured to generate, based on the frequency signal generated by the voltage controlled oscillator over a time interval comprising at least one phase in which the capacitor is charged and comprising at least one phase in which the capacitor is discharged, an indication of the capacitance of the capacitor.

Abstract: According to an embodiment, a multiphase regulator includes a plurality of output phases each of which is operable to deliver a phase current through a separate inductor to a load connected to the output phases via the inductors and an output capacitor. A controller is operable to regulate a voltage delivered to the load by adjusting the phase currents delivered to the load by the output phases, monitor the phase currents delivered to the load by the output phases, determine if the monitored phase currents indicate any of the individual output phases, any of the individual inductors or the output capacitor are faulty even if the total current delivered to the load is within specified limits, synchronously switch the output phases which cause ripples in the phase currents, and detect if any of the phase currents fail to have a ripple current pattern that matches an expected ripple current pattern.

Abstract: A hardware monitor may receive information that identifies a requirement for a system. The requirement may be associated with operation of the system during a runtime operation of the system in an intended operating environment. The hardware monitor may program the one or more hardware components to analyze the system based on the requirement. The hardware monitor may receive a signal from the system during the runtime operation of the system in the intended operating environment. The hardware monitor may analyze the signal during the runtime operation of the system based on the requirement. The hardware monitor may determine, during the runtime operation of the system, that the requirement was violated during the runtime operation of the system based on analyzing the signal. The hardware monitor may output information indicating that the requirement was violated.

Abstract: A chip includes a semiconductor body coupled to a first and a second load terminal. The semiconductor body includes an active region including a plurality of breakthrough cells, each of the breakthrough cells includes: an insulation structure; a drift region; an anode region, the anode region being electrically connected to the first load terminal and disposed in contact with the first load terminal; a first barrier region arranged in contact with each of the anode region and the insulation structure, where the first barrier region of the plurality of breakthrough cells forms a contiguous semiconductor layer; a second barrier region separating each of the anode region and at least a part of the first barrier region from the drift region; and a doped contact region arranged in contact with the second load terminal, where the drift region is positioned between the second barrier region and the doped contact region.

Abstract: In an embodiment, a method includes forming an intentionally doped superlattice laminate on a support substrate, forming a Group III nitride-based device having a heterojunction on the superlattice laminate layer, and forming a charge blocking layer between the heterojunction and the superlattice laminate.

Abstract: A voltage regulator includes a power stage electrically coupled to an input voltage terminal, a controller for controlling the power stage and a shunt resistor of a sense network connected in series between the input voltage terminal and the power stage. In a non-calibration mode, a first level shifting resistor of the sense network is electrically connected in series between a first terminal of the shunt resistor and a first sense pin of the controller and a second level shifting resistor of the sense network is electrically connected in series between a second terminal of the shunt resistor and a second sense pin of the controller. In a calibration mode, the first sense pin and the second sense pin of the controller are electrically connected to the same terminal of the shunt resistor via the first level shifting resistor and the second level shifting resistor of the sense network.

Abstract: A circuit may include a switching element configured to draw a positive current from a source/sink unit when the switching element is turned on, the source/sink unit including an inductance, the inductance emitting an excess positive current after the switching element is turned off. Additionally, the circuit may include a snubber circuit configured to absorb the excess positive current from the inductance of the source/sink unit, and deliver a negative current to the source/sink unit. In one example, the delivered negative current has a lower amperage and a longer duration than the positive current.

Abstract: A method of operating a converter includes a transformer having a first winding and a second winding; a first full-bridge coupled to the first winding of the transformer; and a second full-bridge coupled to the second winding of the transformer. The method includes: injecting an auxiliary current into the second full-bridge, where the injected auxiliary current causes a voltage across a transistor of the first full-bridge to decrease; and turning on the transistor of the first full-bridge a first time period after injecting the auxiliary current.

Abstract: A semiconductor device includes a main transistor and a sense transistor. The main transistor is disposed in a semiconductor body and includes a plurality of sections which are individually controllable via separate gate electrodes disposed above the semiconductor body. The sense transistor is disposed in the same semiconductor body as the main transistor and has the same number of individually controllable sections as the main transistor. Each individually controllable section of the sense transistor is configured to mirror current flowing through one of the individually controllable sections of the main transistor and is connected to the same gate electrode as that individually controllable section of the main transistor. An electronic circuit that includes the semiconductor device and a current sense circuit that outputs a current sense signal representing the current mirrored by the sense transistor is also provided.