Abstract: A semiconductor chip assembly includes first and second semiconductor dies that each include opposite facing upper and lower sides and an outer edge side, and an electrical interposer having opposite facing first and second conductive surfaces and a conductive connection between the conductive surfaces. The second semiconductor die is mounted on top of the first semiconductor die and the interposer such that the lower side of the second semiconductor die faces the first semiconductor die and the interposer, a first lateral section of the second semiconductor die at least partially covers the upper side of the first semiconductor die, and a second lateral section of the second semiconductor die extends past the outer edge side of the first semiconductor die. The first conductive surface is electrically connected to a first terminal that is disposed on a lower side of the second semiconductor die.

Abstract: A method of forming a composite material is provided. The method may include: arranging a suspension in physical contact with a carrier, wherein the suspension may comprise an electrolyte and a plurality of particles of a first component of the composite material; causing the particles of the first component of the composite material to sediment on the carrier, wherein a plurality of spaces may be formed between the sedimented particles; and forming by electroplating a second component of the composite material from the electrolyte in at least a fraction of the plurality of spaces.

Abstract: In one embodiment, the semiconductor device includes a first source of a first doping type disposed in a substrate. A first drain of the first doping type is disposed in the substrate. A first gate region is disposed between the first source and the first drain. A first channel region of a second doping type is disposed under the first gate region. The second doping type is opposite to the first doping type. A first extension region of the first doping type is disposed between the first gate and the first drain. The first extension region is part of a first fin disposed in or over the substrate. A first isolation region is disposed between the first extension region and the first drain. A first well region of the first doping type is disposed under the first isolation region. The first well region electrically couples the first extension region with the first drain.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes oxidizing a substrate to form local oxide regions that extend above a top surface of the substrate. A membrane layer is formed over the local oxide regions and the top surface of the substrate. A portion of the substrate under the membrane layer is removed. The local oxide regions under the membrane layer is removed.

Abstract: A method for calibrating a 3D camera includes determining an actuation of an element by a person and calibrating the 3D camera based on the determining of the actuation.

Abstract: A bonding head includes a pressure plate to press a component (e.g., a semiconductor chip) onto a substrate. The pressure plate includes a holding surface configured to hold the component and to allow the component to be pressed uniformly onto the substrate, thus allowing a particularly reliable connection. The bonding head can further include an apparatus configured to vary the curvature of the holding surface of the pressure plate.

Abstract: The invention relates to an apparatus for preprocessing of pilot symbols for channel estimation. The pilot symbols are transmitted from a base station and are received by a mobile radio, and are available in the mobile radio. The apparatus includes a low-pass filter apparatus for filtering the received pilot symbols, with a setting of the low-pass filter apparatus depending on the relative speed of the mobile radio with respect to the base station.

Abstract: Pulse width modulation (PWM) of a drive current to an organic light emitting diode (OLED) is performed by a circuit subjected to corresponding signaling.

Abstract: The invention relates to a receiver arrangement for a push-pull transmission method. First and second signal detectors, to which a first input signal is fed provide first and second detector signals depending on a comparison of the first input signal with a detector threshold. Third and fourth signal detectors, to which a second input signal is fed provide third and fourth detector signals depending on a comparison of the second input signal with a detector threshold. The first and third detector signals are respectively fed to a data input of a first and second buffer store. The second and fourth detector signals are respectively fed to a reset input of the first and second buffer store. The first and second buffer store are designed for buffer-storing signal pulses contained in the first and second detector signals and forwarding them to a respective output for subsequent further processing in time-delayed fashion after a first delay duration.

Abstract: A method which provides a very simple way of forming a control signal if the frequencies differ too greatly from one another between a useful signal and a reference signal. A control signal is produced which indicates that the frequency error between the frequencies of a useful signal and the frequency of a reference signal exceeds a prescribed error limit value, where the useful signal and the reference signal are used to produce a pulsed signal whose pulse length is proportional to the frequency difference between the useful signal and the reference signal. The pulse length is then compared with a prescribed maximum pulse length, and the control signal is produced if the pulse length exceeds the prescribed maximum pulse length.

Abstract: A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.