Abstract: Adaptive programming method and apparatus for flash memory analog storage. The present invention method is to adjust the voltage of the programming pulse each time based on the result of the previous pulse. The expected change in the programmed value is compared to the measured change, and the difference used to improve the model of that cell after each programming pulse. The algorithm is “adaptive” because the voltage of each pulse is adapted to whatever the cell needs. If the cell is programming too slowly, the voltage is increased dramatically to make it faster. Conversely if the results show that a particular cell is programming too fast, the next voltage pulse is increased by only a small amount (or even decreased if necessary). Because the response of the cell is non-linear, a special analog circuit is used to calculate the optimum voltage for each pulse. As one alternative, a digital calculation may also be used to program the cells.

Abstract: The present invention is a charge pump circuit to reduce and distribute power supply current surges. The charge pump circuit includes a first clock line to provide a first clock thereon, a plurality of delay circuits connected in series, each delay circuit generating a delayed and inverted clock from its input clock on a respective output clock line, and a plurality of charge pump stages connected in series each to store charge thereon. The first clock line is coupled to the first charge pump stage and the plurality of output clock lines are coupled to a respective plurality of remaining charge pump stages. The operation of each charge pump stage is staggered to reduce and distribute the power supply current surges.

Abstract: The present invention relates to a method and apparatus for adjusting the gain of an amplifier circuit. A gain control circuit compares the output of the amplifier with a reference voltage and adjusts a variable resistor, thereby altering the gain of the amplifier.

Abstract: AC coupling and signal amplification using switched capacitors. The use of a switched capacitor to simulate a resistor in amplifier coupling in an integrated circuit processing audio frequency signals avoids the need for external components, reducing cost and eliminating the need for pinouts for the external components. In a system including an anti-aliasing filter, capacitive coupling is used for coupling between amplifiers, with the gain of the second amplifier being set by a feedback capacitor between the amplifier output and its input, as sized relative to the coupling capacitor. The switched capacitor in the feedback loop of the second amplifier preferably couples the output of the anti-aliasing filter back to the amplifier input, thereby minimizing the aliasing from the capacitor switching.

Abstract: An intelligent refreshing method and apparatus for increasing multi-level non-volatile memory charge retention reliability is described. In one embodiment, the apparatus comprises a circuit that is coupled to a multi-level memory cell and a sensing circuit. The sensing circuit senses a voltage of the memory cell and provides a digital value in response thereto. The circuit includes a selection circuit that receives the digital value and at least one trigger voltage, and provides an output trigger voltage responsive to the digital value. The circuit further includes a comparator having a first terminal coupled to receive the output trigger voltage, a second terminal coupled to receive the memory cell voltage, and an output terminal.

Abstract: A power efficient high output swing operational ("HOOP") amplifier for integrated circuit analog signal processing is described. The operational amplifier includes a differential input stage and an output stage. The differential input stage is powered by a regular power supply while the output stage is powered by a voltage multiplier which results in a high voltage output swing without sinking significant power from the voltage multiplier. The high output voltage (e.g., 23 volts) is achieved using low voltage MOS devices. An output isolation technique is utilized to prevent possible latchup and contention. The operational amplifier also features a bias boot scheme to achieve a faster settling time from power up. In addition, the present invention provides realization of frequency compensation with highest possible breakdown and reduced noise coupling.

Abstract: This invention provides column redundancy circuits in a storage array, which circuits are used in a non-volatile memory chip to increase the production yield due to manufacturing defects. The invention includes a scheme to latch and transfer the redundancy information, a redundancy logic circuit, a redundancy column driver, an array architecture with column redundancy, a scheme to program and read the column redundancy memory cells, a scheme to multiplex the fuses, and circuits to use an out-of-bound address as a column redundancy enable/disable signal.

Abstract: A trimbit circuit for flash memory integrated circuits is described. The trimbit circuit is used to store the addresses of bad rows and/or columns in flash memory arrays. Furthermore the trimbit circuit is used to store the trimbits for trimable circuits in the integrated circuit, i.e. voltage references, precision oscillator, etc. The invention includes a row of flash memory trimcells and a trimcell differential amplifier circuit. The trimcell differential amplifier circuit can serially shift in trimbits into a latch and serially shift out trimbits without having to program the flash memory trimcells. The final settings of the trimbits can be programmed by means of a high voltage buffer. A non-overlapping clock generator and additional logic is also included to control the circuit.

Abstract: The present invention is a method of indicating an end of message marker in a plurality of memory cells. The method includes the step of clearing a plurality of memory cells by programming the plurality of memory cells within a first predetermined voltage range to indicate an end of message. The method further includes the step of recording an input signal onto at least a portion of the plurality of memory cells within a second predetermined voltage range. The first and second predetermined voltage ranges are non-overlapping voltage ranges.

Abstract: Methods and apparatus for achieving analog storage in a non-volatile memory array. The array consists of memory cells that utilize Fowler-Nordheim tunneling for erasure and hot electron injection for programming. Writing into a cell is performed by an initial erasure followed by a controlled sequence of program operations during which the cell is programmed in small increments. The stored voltage is read after each program step and when the voltage read back from the cell is equal or just beyond the desired analog level, the sequence of program steps is terminated. The read condition for the cell applies a positive voltage to the drain or common line and a positive voltage to the control gate. The source is connected through a load device to a negative (ground) supply. The output from the cell is the actual voltage that exists at the source node. There is no current sensing or comparison with a reference voltage to determine the output state.

Abstract: Methods and apparatus for achieving analog storage in a non-volatile memory array. The array consists of memory cells that utilize Fowler-Nordheim tunneling for erasure and hot electron injection for programming. Writing into a cell is performed by an initial erasure followed by a controlled sequence of program operations during which the cell is programmed in small increments. The stored voltage is read after each program step and when the voltage read back from the cell is equal or just beyond the desired analog level, the sequence of program steps is terminated. The read condition for the cell applies a positive voltage to the drain or common line and a positive voltage to the control gate. The source is connected through a load device to a negative (ground) supply. The output from the cell is the actual voltage that exists at the source node. There is no current sensing or comparison with a reference voltage to determine the output state.

Abstract: An integrated circuit which operates to store an input analog signal within an analog storage device such as an EEPROM is disclosed. Initially, a target voltage is determined for applying to the memory cell with the target voltage set to about 90% of the input analog signal voltage. A high voltage ramp is applied to the memory cell to set the voltage of the memory cell to the target voltage. A read operation is simultaneously performed while the high voltage ramp is applied to detect the voltage stored on the cell and to terminate the application of the high voltage ramp once the target voltage is reached. Thereafter, a normal read operation is performed on the memory cell to detect the actual voltage of the cell. A new target voltage is determined based upon the actual voltage of the memory cell and the input analog signal voltage. The high voltage ramp is again connected to the memory cell to set the cell to the new target voltage while a simultaneous read operation is performed.

Abstract: A single chip, single or dual message multilevel analog signal recording and playback system is described. In one embodiment, the system comprises a record circuit, an analog storage array, a playback circuit, and a control circuit that independently controls signal storage segments and duration capability. The record circuit receives an audio signal and generates a filtered signal, which is stored in the analog storage array. The playback circuit is coupled to the storage array for retrieving the stored signal for playback. The system further includes a mixer circuit which receives an auxiliary signal and mixes the auxiliary signal with the stored signal during playback. The control circuit also features a novel audio, visual, and input/output functionality.

Abstract: An analog recording and playback system using non-volatile flash memory. An array of flash memory cells is used to store an analog signal and retrieve the stored analog signal on a real-time basis. A plurality of column driver circuits are coupled to the columns of flash memory cells for simultaneous programming and reading. A programming algorithm is used to write the analog signal within an operating range of the flash memory cells since the operating range may shift due to process variations. The system includes trimbit circuits to provide a trimmable initial programming voltage, programming step, programming current, read current, and select gate voltage. The system further includes a Serial Peripheral Interface ("SPI") that interfaces with a host microcontroller. The host microcontroller can send a number of commands to the system through the SPI for efficient message management. These commands include the basic commands to record or playback and various addressing and message cueing options.

Abstract: A trimbit circuit for flash memory integrated circuits is described. The trimbit circuit is used to store the addresses of bad rows and/or columns in flash memory arrays. Furthermore the trimbit circuit is used to store the trimbits for trimable circuits in the integrated circuit, i.e. voltage references, precision oscillator, etc. The invention includes a row of flash memory trimcells and a trimcell differential amplifier circuit. The trimcell differential amplifier circuit can serially shift in trimbits into a latch and serially shift out trimbits without having to program the flash memory trimcells. The final settings of the trimbits can be programmed by means of a high voltage buffer. A non-overlapping clock generator and additional logic is also included to control the circuit.

Abstract: An adaptive amplitude ramp controller that regulates how fast and how high a series of voltages is applied to a targeted non-volatile memory cell. The series of voltages include a coarse ramp pulse and at least one fine ramp pulse. The coarse ramp pulse undergoes a first ramp rate until a particular voltage is reached. Thereafter, it undergoes a second ramp rate until the cycle associated with the coarse ramp pulse is completed or a target voltage is reached. Programming of the non-volatile memory cell occurs during this portion of the course ramp pulse. Thereafter, the adaptive amplitude ramp controller produces at least one fine ramp pulse. The fine ramp pulse is quickly ramped up at a third ramp rate and then undergoes a fourth ramp rate until the final desired voltage of the non-voltage memory cell is generally reached.

Abstract: This invention utilizes the small cell size of the NAND storage cell structure in an analog storage and playback device. This is achieved, in part, by using a special, zero current storage cell, in which in the read mode, the cell loading current is waveshaped to attain an optimal dynamic range and to avoid the resistive effects of series parasitic resistances of other transistors in the source node or drain node, and to avoid the transistor conductance variations of all the transistors in the read path. The loading current is waveshaped to reduce possible overshoot and settling effects to achieve the fine output voltage resolution in an optimal sensing time. Details of the method and alternate embodiments are disclosed.

Abstract: A circuit and method for adjusting the ramp voltage applied to a control gate of a non-volatile memory cell to improve programming accuracy. The method involves measuring an amount of additional voltage realized at a source of the floating gate transistor. Thereafter, a preset compensation ratio may be selected to reduce a ramp voltage applied to the control gate of the memory cell by an amount necessary to lessen the amount of additional voltage realized at the source of the floating gate transistor. This will reduce inaccurate measurement of voltages during the read-while-write voltage program technique. A voltage control circuit is connected to the control gate for precise reduction of the ramp voltage.

Abstract: The present invention discloses a circuit for controlling operation of a functional circuit in a device based on a test result during testing. The circuit comprises a first storage element configured to be in one of a first state and a second state according to the test result, and a first sensing element coupled to the first storage element for generating a first signal used to control the operation of the functional circuit.

Abstract: The present invention is a method and apparatus for reading a storage cell configured in a negative feedback mode to provide linear variation of cell current with the threshold of the cell. The apparatus comprises a floating gate storage cell having a source, a gate, a floating gate and a drain. The source of the floating gate storage cell has a first predetermined reference voltage and the gate of the floating gate storage cell has a predetermined second reference voltage. The apparatus also comprises first circuitry driving the voltage on the drain of the floating gate storage cell to a third predetermined reference voltage, the first, second and third predetermined reference voltages being selected to not change a threshold voltage of the storage cell. The apparatus further comprises second circuitry providing an output proportional to the current passing through the floating gate storage cell while the first, second and third predetermined reference voltages are applied.