Abstract: A multi-thread processor computes a function requiring only modular additions and multiplications. Memories store constants, multi-bit elements, and multiple instruction sets. A multiplier receives first and second multiplier operands, generates their product, which is fed to an adder as a first operand and added to a second adder operand, the sum being stored in an accumulator memory. Each instruction set is executed on a successive clock, and includes instructions for defining respective addresses in the memories from which constants, elements and sums are to be accessed. A scheduler maintains a schedule of threads executable by the processor in parallel, and is configured on each successive clock to cycle through the threads and initiate a first available thread. Selectors responsive to instructions received from the program memory select the required multiplier and adder operands.
Type:
Grant
Filed:
January 30, 2023
Date of Patent:
November 4, 2025
Assignee:
INGONYAMA LTD.
Inventors:
Michael Asa, Omer Shlomovits, Daniel Shterman, Yuval Domb
Abstract: A multi-thread processor computes a function requiring only modular additions and multiplications. Memories store constants, multi-bit elements, and multiple instruction sets. A multiplier receives first and second multiplier operands, generates their product, which is fed to an adder as a first operand and added to a second adder operand, the sum being stored in an accumulator memory. Each instruction set is executed on a successive clock, and includes instructions for defining respective addresses in the memories from which constants, elements and sums are to be accessed. A scheduler maintains a schedule of threads executable by the processor in parallel, and is configured on each successive clock to cycle through the threads and initiate a first available thread. Selectors responsive to instructions received from the program memory select the required multiplier and adder operands.
Type:
Application
Filed:
January 30, 2023
Publication date:
August 1, 2024
Applicant:
INGONYAMA LTD.
Inventors:
Michael ASA, Omer SHLOMOVITS, Daniel SHTERMAN, Yuval DOMB
Abstract: A hardware accelerator computes a scalar dot product given by ?i=0N?1diPi where di is a scalar of length b bits and Pi is an element in a group. The hardware accelerator includes a plurality A of accumulators addressed by corresponding contiguous partitions of the scalar di, each partition being of length c such that A = ? b c ? and each accumulator containing a plurality B of buckets where B=2c. The value of Pi is entered into each empty accumulator bucket whose value corresponds to the weight of the respective partition associated with the corresponding accumulator or is added to a non-zero value that is already in the bucket, the sum replacing the previous value. An accumulator sums the values in the respective buckets of each accumulator so as to derive A sums, and sums the A computed sums to derive the scalar dot product.
Type:
Application
Filed:
September 6, 2022
Publication date:
March 7, 2024
Applicant:
INGONYAMA LTD.
Inventors:
Daniel SHTERMAN, Omer SHLOMOVITS, Michael ASA, Yuval DOMB