Abstract: An integrated circuit includes a patterned aluminum based interconnect clad on the top and side portions with a layer of transition metal. The cladding of transition metal prevents the formation of both vertical hillocks and lateral protrusions. Preventing these formations increases the reliability of an interconnect by significantly reducing passivation cracking and electrical shorting between interconnects which result from vertical hillock and lateral protrusion formations.

Abstract: A metallic interconnect includes a fuse portion that is readily vaporized upon exposure to the radiant energy of a laser. A layer of optically absorptive material is formed on top of an aluminum based metallic interconnect and together they are formed by a photolithographic and etch technique into a fuse portion. A low energy laser having a Gaussian energy distribuution focused on the absorptive layer produces heat in the absorptive layer. The heat is transferred to the underlying aluminum based interconnect. The concentration of energy made possible by the absorptive layer allows the low energy laser to blow the fuse thereby producing an electrical open in the interconnect without damaging surrounding silicon substrate and/or polysilicon structures below or nearby the metal fuse.

Abstract: A process of manufacturing selectively restructurable conductive links between circuit elements and corresponding spare elements on a semiconductor. A continuous green light laser directed at a non-conductive amorphous region in the links causes the region to recrystallize. This makes the link electrically conductive thereby joining the circuit elements to a corresponding spare element on the semiconductor. The method permits for high density packing of circuit elements and creates a link without producing bulk material movement.

Abstract: A metallic interconnect includes a fuse portion that is readily vaporized upon exposure to the radiant energy of a laser. A layer of optically absorptive material is formed on top of an aluminum based metallic interconnect and together they are formed by a photolithographic and etch technique into a fuse portion. A low energy laser having a Gaussian energy distribution focused on the absorptive layer produces heat in the absorptive layer. The heat is transferred to the underlying aluminum based interconnect. The concentration of energy made possible by the absorptive layer allows the low energy laser to blow the fuse thereby producing an electrical open in the interconnect without damaging surrounding silicon substrate and/or polysilicon structures below or nearby the metal fuse.

Abstract: A method of measuring the phosphorus concentration in phosphosilicate and borophosphosilicate films using infrared spectroscopy in conjuction with derivative spectroscopic techniques. This method is easily adapted for use with a Fourier Transform spectrometer. A spectrum of the film is taken with a dual beam infrared spectrometer. The second derivative of the spectrum is plotted to rersolve close peaks. Amplitudes of the P.dbd.O band at 1316 cm.sup.-1 and the O--Si--O band at 818 cm.sup.-1 are measured. A ratio between these amplitudes is calculated. The ratio is then matched to a calibration curve to determine the phosphorus concentration.

Abstract: Column circuitry for a CMOS static RAM includes a bit line clamp combined with a bit line current source regulated by a voltage reference which tracks changes in transistor characteristics. Separate data read and data write lines are provided, with a differential amplifier for each pair of bit lines. The data read lines are coupled to compensated current source loads, and the differential amplifiers are coupled to switching transistors which are also compensated for transistor characteristic changes. Each bit line pair has a sneak capacitance prevention transistor so that in non-selected columns the bit line pairs are coupled together allowing the memory cells therein to pull down all of the bit lines. This isolates the read lines from unwanted capacitance in the differential amplifiers of each of the non-selected columns. Further, a VCC protection circuit is provided.

Abstract: A titanium silicide/titanium nitride process is disclosed wherein the thickness of the titanium nitride can be regulated with respect to the titanium silicide. In particular, a control layer is formed in the contact opening during a reactive cycle to form a relatively thin (20 to 50 angstrom) control layer. Titanium is thereafter deposited and in another thermal reaction the control layer retards the development of titanium silicide without retarding the development of titanium nitride so that the thickness of titanium silicide is kept small. A double titanium process can also be used.

Abstract: An amplifier for a semiconductor circuit provides two circuit paths between VCC and ground, each including the source-drain path of a corresponding primary transistor. Two inpedances are coupled to respective inputs. The primary transistors are kept in saturation so that the voltage differential between the inputs is minimized but a large voltage differential is developed at outputs located along the two circuit paths. Also, a clamp circuit has a common node coupling the gate electrodes of the primary transistors together. Secondary transistors are included to mimic voltage changes on either input.

Abstract: An input buffer has input and output inverters. An n-channel transistor is coupled as a source follower between the inverters. The buffer receives a TTL input and provides a CMOS output. The source follower transistor has a large channel width and provides substantial pullup. The output inverter stage can be made larger. A p-channel transistor in parallel with the n-channel source follower transistor permits the internal node to reach a full Vcc level. Another n-channel transistor driven by the input signal permits the node to reach ground.

Abstract: To locate soft cells in a memory cell array, a known logic pattern is written in the memory array. The word lines for the array are then sequentially subjected to a nonstandard test signal such as a slowly varying voltage. Word lines are returned to VCC and the array is then interrogated to identify memory cells which have flipped logic states. These cells are identified as soft or potentially defective cells. The process can be repeated with the logically opposite logic pattern being initially stored in the array. Apparatus is provided for implementing this process on a standard RAM memory cell array. An access pad is added for receipt of an externally generated test signal. A control circuit selectively couples the test signal to the word lines for the memory array.

Abstract: An improved process in making a polysilicon resistor suitable for use as a load resistor in a static memory wherein after the doping of the polysilicon, the device is annealed by exposing it to a rapid increase of ambient temperature (up to between 900 and 1200.degree. C.), maintaining the high ambient temperature for a controlled time (about 5 seconds) and then lowering the ambient tempertature at a rapid rate. This decreases resistances by one order of magnitude and significantly decreases the temperature activation energy of the resistor. This permits static memory cells to retain data even though the cell has high leakage currents, thereby improving final test yields.

Abstract: An improved row decoding technique for use in a static RAM. Three stages of row decoders are utilized to further decode partially decoded row address signals and combine the decoded signals with a column address signal to enable selected rows of the memory array. To optimize decoding speed, each stage comprises gates which receive only two inputs from the prior stage and the stages are arranged to allow for sharing of signals between adjacent decoders.

Abstract: An improved load resistor for a VLSI memory cell is formed in polysilicon by having P-type (such as boron) impurities in a middle region and n-type (such as phosphorous or arsenic) impurities on the sides, with the concentrations being in a range so that the thermal activation energy is below about 0.5 eV. Further, the middle region can be doped additionally with arsenic or phosphorous in an amount equal to or less than the boron. This gives good leakage current masking over a range of -55.degree. to +125.degree. C. without drawing excessive current, and is less sensitive to impurities.

Abstract: In a DRAM, current surges during sense and restore operations are compensated. Peak current through sense amplifiers is stabilized through initiation of the sense and restore operations during the chip active period and completion of the sense and restore operation during the chip precharge period. The delay between first and second sensing signals is controlled to be longer for those temperature and power supply conditions under which the chip is operating fastest. Correspondingly, the delay between first and second sensing signals is made shorter for those temperature and power supply conditions under which the chip is operating slowest. Overall peak current is limited to that drawn through small transistors used to begin turning on the sense amplifier. The duration of the second sensing signal is responsive to the temperature and power supply variation so it endures for an acceptable period in which to complete the sense and restore function.

Abstract: In making a polysilicon resistor in a polycide line, a thick oxide is established selectively to shield lightly doped polysilicon first from heavy doping and then from the silicide. Before adding silicide, a selected region of polysilicon broader than and including the site of the poly resistor is exposed, lightly doped, and then oxidized to establish a thick oxide, while other areas are protected by nitride. Then the nitride and any thin oxide on top of the polysilicon outside the broad area are removed, and the exposed polysilicon is heavily doped for low resistivity. The thick oxide shields the underlying lightly doped polysilicon from the heavy doping. Silicide is then added. Definition of the polysilicon resistor follows preferably using a two step process. When the silicide is etched, the thick oxide on top of the broad polysilicon area acts as an etch stop. Then the thick oxide and polysilicon resistor are etched.

Abstract: A poly layer on a substrate is covered with nitride. A reverse tone load implant mask and etch opens an area, which is then boron implanted. Controlled oxidation follows to grow oxide on the boron-doped region only, thereby thinning the poly there. Strip the nitride and then dope the poly layer. The oxide shields the boron-doped region from further substantial doping. Next, apply a poly definition photoresist mask. Etch the exposed oxide and poly to define a poly line having a boron-doped resistor therein. The difference in etch rates between heavily doped and lightly doped poly is compensated for by the adjustment of thickness of the boron-doped region. Hence, the etch for both types of poly concludes at about the same time, leaving the underlying layers substantially intact. Sources and drains may be implanted thereafter without an additional load implant mask.

Abstract: A CMOS substrate bias generator including a PMOS charge pump and a regulator for controlling the operation of the substrate bias generator. The substrate bias generator further includes an input circuit, a reference circuit to provide a reference voltage, a comparison circuit to compare voltage levels between the input and the reference circuit, and output circuitry to provide a signal from the comparison circuitry to the substrate bias generator. The comparison circuitry further includes hysteresis circuitry tending to preserve voltage at a node in the comparison circuit despite an imbalance between the input circuit and the reference circuit.

Abstract: An improved semiconductor structure and the method for fabricating such is disclosed. The invention relates to the use of thick-oxide for improved field-shield isolation especially as applied to dynamic RAMS's and also to its integration into an improved CMOS process. The improved structure has increased isolation characteristics between adjacent memory cells and still allows for lessened spacing between cells. The corresponding process determines the spacing between cells through etching and eliminates several steps by utilizing one mask for several purposes including defining the active transistor areas and the first polysilicon layer and by extending the use of the first polysilicon layer for field-shield isolation between cells. Additional advantages are disclosed including a higher body effect in the isolation transistors, use of a nitride dielectric layer, and a higher, stable threshold voltage in the isolation transistors.

Abstract: Method and apparatus for controlling latch-up in a CMOS circuit senses a power supply transition, clamps the substrate to ground in response to sensing a power supply transition, and releases the clamp after the power supply transition. A charge pump pumps the substrate illustratively to -3 volts. The charge pump, clamping transistor and related elements are on the same CMOS substrate where latch-up is to be controlled. The substrate to ground capacitance of the substrate is increased to prevent localized substrate voltage disturbances which may induce latch-up.

Abstract: A folded bit line-shared sense amplifier arrangement is described for sensing the logic state of an accessed memory cell in a dynamic MOS random access memory. In the preferred embodiment, a shared sense amplifier is positioned between and coupled to first and second bit lines via first and second isolation transistors. The same shared sense amplifier is also positioned between and coupled to third and fourth bit lines via third and fourth isolation transistors. When the state of an accessed memory cell is to be sensed, its memory cell capacitor is coupled to a selected bit line and a dummy cell capacitor is coupled to the bit line adjacent the selected bit line. A decoding circuit selectively activates the shared sense amplifier to sense a difference in voltage between the selected bit line and its adjacent bit line so as to determine the logic state associated with the accessed memory cell. Then, the sense amplifier latches into this logic state for reading by the input/output buss lines.