Abstract: A method and a circuit configuration for operation of a bus system. A bus includes a bus control unit which controls only an arbitration and when time is exceeded during a data transmission. An actual data transmission is determined in a respective active master unit and an addressed slave unit. A characteristic of a bus cycle, such as a data length, access to a data area or a control area and a waiting cycle, is transmitted in encoded form through a multiplicity of control lines.
Inventors:
Thomas Niedermeier, Peter Rohm, Richard Schmid, David Flynn, Peter Klapproth, Frederik Zandveld, Jacobus Christophorus Koot, Andrew Michael Jones, James Graham Matthew, Bruno Douady
Abstract: A cascaded array of devices, each having electrical signal processing elements arranged to process simultaneously the same input data, is provided with inter-device connections including signal delay so that an intermediate result of processing by a second device is combined with an output which was derived from a first device at a time related to that at which input data was input to the second device for use in forming its intermediate result.
Type:
Grant
Filed:
May 19, 1987
Date of Patent:
May 30, 1989
Assignee:
INMOS Ltd.
Inventors:
Mohamad H. Yassaie, Anthony D. King-Smith, Clive M. Dyson
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