Abstract: Wideband polar receivers and method of operation are described. A phase-modulated input signal is received at a polar receiver that includes an injection-locked oscillator. The injection-locked oscillator includes a plurality of injection points. Based on the frequency of the input signal, a particular Nth harmonic is selected, and the input signal is injected at the set of injection points corresponding to the selected Nth harmonic. The injection-locked oscillator generates an oscillator output signal, and the phase of the input signal is determined from the phase of the oscillator output signal. In some embodiments, the oscillator output signal is frequency-multiplied by N, mixed with the input signal, and filtered for use in amplitude detection. The input signal is decoded based on the phase and amplitude information.

Abstract: Systems and methods are provided for aligning amplitude and phase signals in a polar receiver. A receiver generates digital amplitude and phase signals representing the amplitude and phase of a modulated input signal. At least one of the digital signals is filtered using a fractional delay filter with a variable delay. The delay of the fractional delay filter is adjusted to align the amplitude and phase signals. In some embodiments, an error vector magnitude is determined by comparing in-phase and quadrature values of the signal with values corresponding to a constellation point, and the delay is adjusted based on the error vector magnitude. The fractional delay filter may be a finite impulse response filter with coefficients stored in a lookup table that correspond to different delays.

Abstract: A predistortion circuit receives an input polar signal to be transmitted, including an input amplitude signal and an input phase signal. The input polar signal is predistorted using at least one predistortion parameter selected from a lookup table. A phase-and-amplitude modulated radio-frequency signal is generated corresponding to the predistorted polar signal. A copy of the generated radio-frequency signal is provided to a polar receiver. The polar receiver is operated to generate, from the copy of the radio-frequency signal and without information relating to the generated transmit signal, a feedback polar signal including a feedback amplitude signal and a feedback phase signal. The feedback polar signal is compared to the input polar signal, the lookup table is updated in response to the comparison.

Abstract: Circuitry and methods are described for digital signal demodulation. In a configurable receiver, a method includes receiving a radio frequency signal at the configurable receiver, operating the configurable receiver in a first mode, the first mode including providing the radio frequency signal to an amplitude detection circuit to determine an amplitude, providing the radio frequency signal to a phase detection circuit to determine a phase, and providing the amplitude and phase to a coordinate rotation digital computer (CORDIC) logic circuit, and operating the configurable receiver in a low power mode upon receiving an indication to selectively disable the amplitude detection circuit, the low power mode including providing the radio frequency signal to the phase detection circuit to determine the phase, and providing the phase and a predetermined constant value in lieu of the amplitude to the CORDIC logic circuit.

Abstract: Systems and methods are provided for converting time measurements to digital value representing phase. Such systems and methods use a ring oscillator to create a coarse measurement of the time difference between first and second rising edges of a modulated signal. A two-dimensional Vernier structure is used to create a fine resolution measurement of the error in the coarse measurement. The coarse and fine measurements are combined to calculate a digital time measurement. A digital time output is calculated as the difference in successive digital time measurements. An offset digital time output is calculated as a difference in a digital time output in relation to a carrier period offset. The offset digital time output is scaled and accumulated to calculate the integrated time signal. The integrated time signals are synchronized to the carrier frequency to output a series of final phase measurements.

Abstract: A digitally controlled oscillator (DCO) modulation apparatus and method provides a wideband phase-modulated signal output. An exemplary modulator circuit uses an oscillator in a phase-locked loop. The circuit receives a wrapped-phase input signal, unwraps the wrapped-phase input signal to generate an unwrapped-phase signal, and differentiates the unwrapped-phase signal. The wrapped-phase input signal and the differentiated unwrapped-phase signal are both injected into a feedback loop of the modulator circuit. The feedback loop may include a multi-modulus frequency divider with a frequency divisor that is temporarily incremented or decremented to cancel out abrupt phase jumps associated with the wrapped-phase to unwrapped-phase conversion.

Abstract: An inductor isolation apparatus and method to reduce interaction between inductors on an integrated circuit.

Abstract: Wideband polar receivers and method of operation are described. A phase-modulated input signal is received at a polar receiver that includes an injection-locked oscillator. The injection-locked oscillator includes a plurality of injection points. Based on the frequency of the input signal, a particular Nth harmonic is selected, and the input signal is injected at the set of injection points corresponding to the selected Nth harmonic. The injection-locked oscillator generates an oscillator output signal, and the phase of the input signal is determined from the phase of the oscillator output signal. In some embodiments, the oscillator output signal is frequency-multiplied by N, mixed with the input signal, and filtered for use in amplitude detection. The input signal is decoded based on the phase and amplitude information.

Abstract: Wideband polar receivers and method of operation are described. A phase-modulated input signal is received at a polar receiver that includes an injection-locked oscillator. The injection-locked oscillator includes a plurality of injection points. Based on the frequency of the input signal, a particular Nth harmonic is selected, and the input signal is injected at the set of injection points corresponding to the selected Nth harmonic. The injection-locked oscillator generates an oscillator output signal, and the phase of the input signal is determined from the phase of the oscillator output signal. In some embodiments, the oscillator output signal is frequency-multiplied by N, mixed with the input signal, and filtered for use in amplitude detection. The input signal is decoded based on the phase and amplitude information.

Abstract: A digitally controlled oscillator (DCO) modulation apparatus and method provides a wideband phase-modulated signal output. An exemplary modulator circuit uses an oscillator in a phase-locked loop. The circuit receives a wrapped-phase input signal, unwraps the wrapped-phase input signal to generate an unwrapped-phase signal, and differentiates the unwrapped-phase signal. The wrapped-phase input signal and the differentiated unwrapped-phase signal are both injected into a feedback loop of the modulator circuit. The feedback loop may include a multi-modulus frequency divider with a frequency divisor that is temporarily incremented or decremented to cancel out abrupt phase jumps associated with the wrapped-phase to unwrapped-phase conversion.

Abstract: Determining a speed and a range of an object by generating at least a first, second, and third interval-specific tone phase signals associated with at least three successive time intervals, wherein at least two of the generated and transmitted tones are different frequencies; determining at least a first, second and third interval-specific average phase value from the respective interval-specific tone phase signals; and then determining a range estimate of the object and determining a speed estimate of the object using at least two phase differences between the at least first, second and third interval-specific average phase values.

Abstract: Circuitry and methods are described for digital signal demodulation. In a polar receiver, a modulated radio-frequency input signal is provided to frequency division circuitry, which may include a harmonic injection-locked oscillator (ILO). The phase of the frequency-divided output is measured using a self-triggered time-to-digital converter (TDC), which may be a Vernier TDC. A subtractor subtracts a period offset from the output of the TDC to generate an offset digital time output, and a digital integrator integrates the offset digital time output. The integrated time signal represents the phase of the radio-frequency input signal and can be used to determine a symbol, such as a phase-shift keying (PSK) or quadrature amplitude modulation (QAM) symbol, conveyed by the modulated radio-frequency input signal.

Abstract: A DAC using current mirrors suitable for use in a modulator. Embodiments include a current-generating circuit to provide an information signal; a bias current source; a current mirror having a mirror input transistor connected to the current generating circuit and the bias current source, and being driven by the bias current and the varying current signal and having a corresponding varying voltage signal at a control terminal; a signal shaping filter interposed between the mirror input transistor and an output mirror transistor configured to limit a bandwidth of the varying voltage signal; the output mirror transistor configured to generate a band-limited varying current signal and a mirrored bias current; and, a mirrored bias current reduction circuit connected to the output mirror transistor configured to reduce the mirrored bias current.

Abstract: A digitally controlled oscillator (DCO) modulation apparatus and method provides a wideband phase-modulated signal output. An exemplary modulator circuit uses an oscillator in a phase-locked loop. The circuit receives a wrapped-phase input signal, unwraps the wrapped-phase input signal to generate an unwrapped-phase signal, and differentiates the unwrapped-phase signal. The wrapped-phase input signal and the differentiated unwrapped-phase signal are both injected into a feedback loop of the modulator circuit. The feedback loop may include a multi-modulus frequency divider with a frequency divisor that is temporarily incremented or decremented to cancel out abrupt phase jumps associated with the wrapped-phase to unwrapped-phase conversion.

Abstract: A receiver includes a harmonic injection-locked oscillator, which receives an RF modulated signal and provides an output to two parallel signal paths. A fundamental injection-locked oscillator is provided on one of the signal paths. A phase discriminator detects a phase difference between signals that have passed through the first and second signal paths. At least one of the signal paths includes an amplitude limiting circuit. One or more of the signal paths may include an adjustable delay circuit.

Abstract: A method of generating inphase and quadrature signals from a polar receiver providing a phase derivative signal and an envelope magnitude signal comprising receiving an estimated phase derivative signal; generating an estimated phase signal; mapping the estimated phase signal to an angular value; converting the estimated phase signal to an inphase signal and a quadrature signal based on the angular value; and, providing the inphase signal and quadrature signal to a demodulation circuit.

Abstract: A radio-frequency peak amplitude detection circuit includes a load capacitor, a current source that charges the load capacitor and set the bias current for the field effect transistors, and a pair of field effect transistors. The gates of the field effect transistors are biased at a level below the threshold voltage of the transistors. The transistors are arranged in parallel with the capacitor and are operable to drain the capacitor at a rate determined by a differential input at the gates of the transistors. The voltage across the load capacitor is low-pass filtered and has a voltage level representative of the amplitude of the differential input signal.

Abstract: A DAC using current mirrors suitable for use in a modulator. Embodiments include a current-generating circuit to provide an information signal; a bias current source; a current mirror having a mirror input transistor connected to the current generating circuit and the bias current source, and being driven by the bias current and the varying current signal and having a corresponding varying voltage signal at a control terminal; a signal shaping filter interposed between the mirror input transistor and an output mirror transistor configured to limit a bandwidth of the varying voltage signal; the output mirror transistor configured to generate a band-limited varying current signal and a mirrored bias current; and, a mirrored bias current reduction circuit connected to the output mirror transistor configured to reduce the mirrored bias current.

Abstract: A receiver includes a harmonic injection-locked oscillator, which receives an RF modulated signal and provides an output to two parallel signal paths. A fundamental injection-locked oscillator is provided on one of the signal paths. A phase discriminator detects a phase difference between signals that have passed through the first and second signal paths. At least one of the signal paths includes an amplitude limiting circuit. One or more of the signal paths may include an adjustable delay circuit.

Abstract: A DAC using current mirrors suitable for use in a modulator. Embodiments include a current-generating circuit to provide an information signal; a bias current source; a current mirror having a mirror input transistor connected to the current generating circuit and the bias current source, and being driven by the bias current and the varying current signal and having a corresponding varying voltage signal at a control terminal; a signal shaping filter interposed between the mirror input transistor and an output mirror transistor configured to limit a bandwidth of the varying voltage signal; the output mirror transistor configured to generate a band-limited varying current signal and a mirrored bias current; and, a mirrored bias current reduction circuit connected to the output mirror transistor configured to reduce the mirrored bias current.