Abstract: The semiconductor device includes a substrate, a first nitride semiconductor layer disposed on the substrate, a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a bandgap greater than that of the first nitride semiconductor layer. The semiconductor device further includes a first gate conductor disposed on a first region of the second nitride semiconductor layer, a first source electrode disposed on a first side of the first gate conductor, a first field plate disposed on a second side of the first gate conductor, a first conductive terminal and a second conductive terminal disposed on a second region of the second nitride semiconductor layer, and a resistor formed in the first nitride semiconductor layer and electrically connected between the first conductive terminal and the second conductive terminal, wherein the resistor comprises at least one conductive region.

Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode, a drain electrode, a gate electrode and a single field plate. The source electrode, the drain electrode, and the gate electrode are disposed on the second nitride-based semiconductor layer. The gate electrode is between the source and drain electrodes. The single field plate is disposed over the gate electrode and extends toward the drain electrode. The field plate has a first end part, a second end part and the central part. The first and the second end parts are located at substantially the same height. Portions of the central part are in a position lower than that of the first and second end parts, and the first end part extends laterally in a length greater than a width of the gate electrode.

Abstract: A semiconductor device includes a gate electrode, first and second passivation layers, first and second field plates. The gate electrode is disposed above nitride-based semiconductor layers. The first passivation layer covers the gate electrode. The first field plate is disposed on the first passivation layer. The first passivation layer has a first portion covered with the first field plate and a second portion free from coverage of the first field plate. The second passivation layer covers the first field plate. The second field plate is disposed over the second passivation layer. The second passivation has a first portion covered with the second field plate and a second portion is free from coverage of the second field plate. A thickness difference between the first and second portions of the first passivation layer is less than a thickness difference between the first and second portions of the second passivation layer.

Abstract: The present invention provides a high efficiency, high density GaN-based power converter comprising: a transformer; a magnetic coupler; a primary switch; a secondary switch; a primary controller; a secondary controller; a multi-layered print circuit board (PCB) comprising: one or more planar coils respectively formed on one or more PCB layers and aligned with each other for constructing the transformer and the coupler; and a plurality of conducting traces and vias for providing electrical connection among the transformer, the coupler, a primary switch, a secondary switch, a primary controller and a secondary controller. The power converter further comprises a pair of ferrite cores being fixed to a top surface and a bottom surface of the PCB respectively and commonly shared by the transformer and the coupler.

Abstract: The present invention provides a high efficiency, high density GaN-based power converter comprising: a transformer; a magnetic coupler; a primary switch; a secondary switch; a primary controller; a secondary controller; a multi-layered print circuit board (PCB) comprising: one or more planar coils respectively formed on one or more PCB layers and aligned with each other for constructing the transformer and the coupler; and a plurality of conducting traces and vias for providing electrical connection among the transformer, the coupler, a primary switch, a secondary switch, a primary controller and a secondary controller. The power converter further comprises a pair of ferrite cores being fixed to a top surface and a bottom surface of the PCB respectively and commonly shared by the transformer and the coupler.

Abstract: The present invention provides a multi-functional printed circuit board (PCB) for assembling a plurality of components of a power converter in to a single package. The PCB comprises: one or more planar coils respectively formed on one or more PCB layers and aligned with each other for constructing the transformer and the coupler; and a plurality of conducting traces and vias for providing electrical connection among the plurality of components of the power converter.

Abstract: The present invention provides a high efficiency, high density GaN-based power converter comprising: a transformer; a magnetic coupler; a primary switch; a secondary switch; a primary controller; a secondary controller; a multi-layered print circuit board (PCB) comprising: one or more planar coils respectively formed on one or more PCB layers and aligned with each other for constructing the transformer and the coupler; and a plurality of conducting traces and vias for providing electrical connection among the transformer, the coupler, a primary switch, a secondary switch, a primary controller and a secondary controller. The power converter further comprises a pair of ferrite cores being fixed to a top surface and a bottom surface of the PCB respectively and commonly shared by the transformer and the coupler.

Abstract: The present invention provides a multi-functional printed circuit board (PCB) for assembling a plurality of components of a power converter in to a single package. The PCB comprises: one or more planar coils respectively formed on one or more PCB layers and aligned with each other for constructing the transformer and the coupler; and a plurality of conducting traces and vias for providing electrical connection among the plurality of components of the power converter.

Abstract: A nitride-based semiconductor device includes a buffer, a first nitride-based semiconductor layer, a shield layer, a second nitride-based semiconductor layer, S/D electrodes, and a gate electrode. A first nitride-based semiconductor layer is disposed over the buffer. A shield layer is disposed between the buffer and the first nitride-based semiconductor layer and includes a first isolation compound that has a bandgap greater than a bandgap of the first nitride-based semiconductor layer, in which the first isolation compound is made of at least one two-dimensional material which includes at least one metal element. A second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap less than the bandgap of the first isolation compound and greater than the bandgap of the first nitride-based semiconductor layer. The pair of S/D electrodes and the gate electrode are disposed over the second nitride-based semiconductor layer.

Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a barrier layer, a third nitride semiconductor layer and a gate structure. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a bandgap greater than that of the first nitride semiconductor layer. The barrier layer is disposed on the second nitride semiconductor layer and has a bandgap greater than that of the second nitride semiconductor layer. The third nitride semiconductor layer is doped with impurity and disposed on the barrier layer. The gate structure is disposed on the third nitride semiconductor layer.

Abstract: A semiconductor device includes a semiconductor substrate, first and second nitride-based semiconductor layers, S/D electrodes, a gate electrode, and a first passivation layer. The first nitride-based semiconductor layer is disposed over the semiconductor substrate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a 2DEG region. The S/D electrodes is disposed over the second nitride-based semiconductor layer. The gate electrode is disposed between the S/D electrodes. The first passivation layer is disposed over the second nitride-based semiconductor layer. Edges of the first and second nitride-based semiconductor layers and the first passivation layer collectively form a stepped sidewall over the semiconductor substrate.

Abstract: A flip-chip semiconductor package with improved heat dissipation capability and low package profile is provided. The package comprises a heat sink having a plurality of heat dissipation fins and a plurality of heat dissipation leads. The heat dissipation leads are connected to a plurality of thermally conductive vias of a substrate so as to provide thermal conductivity path from the heatsink to the substrate as well as support the heatsink to relieve compressive stress applied to a semiconductor die by the heatsink. The package further comprises an encapsulation layer configured to cover the heat dissipation leads of the heat sink and expose the heat dissipation fins of the heat sink.

Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer, a doped group III-V semiconductor layer and a gate layer. The first nitride semiconductor layer has a first surface. The second nitride semiconductor layer is formed on the first surface of the first nitride semiconductor layer and has a greater bandgap than that of the first nitride semiconductor layer. The doped group III-V semiconductor layer is over the second nitride semiconductor layer. The doped group III-V semiconductor layer includes a first portion and a second portion having different thicknesses. The gate layer is disposed on the first portion and the second portion of the doped group III-V semiconductor layer.

Abstract: A CVD apparatus for manufacturing a III-nitride-based layer having a rotating wafer carrier positioned inside a reaction chamber that receives a mixture of a nitrogen gas source and a group III element gas source. Recesses are formed within the wafer carrier, each including a satellite disc of thickness x for accepting a wafer of thickness t. The satellite disc includes a peripheral notch of height a, and a notch thickness of x?a=b. A peripheral retaining ring includes a vertical rise portion extending a distance of e+f and a laterally-extending portion, the laterally-extending portion engaging the satellite disc notch. A gap c is formed between the substrate and a surface of the satellite disc. The relationship of a+b+c+t=b+e+f is satisfied such that laminar flow occurs in the region of the retaining ring.

Abstract: The subject application provides a power converter with lossless current sensing capability. The power converter comprises: a transformer, a primary switch for conducting or blocking a current flowing in a primary winding of the transformer, a controller configured to generate a first control signal through a first control node to control the primary switch; and a current sensing circuit configured for sensing a current flowing in the primary winding. The current sensing circuit comprises a current sensing switch that is configured to be normally open and has a gate length smaller than a gate length of the primary switch. A relatively simple current sensing circuit is achieved and the overall power efficiency is improved.

Abstract: A semiconductor device includes a substrate, a first GaN-based high-electron-mobility transistor (HEMT), a second GaN-based HEMT, a first interconnection, and a second interconnection is provided. The substrate has a plurality of first-type doped semiconductor regions and second-type doped semiconductor regions. The first GaN-based HEMT is disposed over the substrate to cover a first region on the first-type doped semiconductor regions and the second-type doped semiconductor regions in the substrate. The second GaN-based HEMT is disposed over the substrate to cover a second region. The first region is different from the second region. The first interconnection is disposed over and electrically connected to the substrate, forming a first interface. The second interconnection is disposed over and electrically connected to the substrate, forming a second interface. The first interface is separated from the second interface by at least two heterojunctions formed in the substrate.

Abstract: The subject application provides an apparatus and method for measuring dynamic on-resistance of a device under test (DUT) comprising a control terminal electrically connected to an output of a first controlling module being configured to generate a first control signal to switch on and off the DUT. The apparatus comprises a switching device and a second controlling module configured to: receive the first control signal from the first controlling module and generate a second control signal to switch on and off the switching device such that the switching device is turned on later than the DUT for a first time interval and turned off earlier than the DUT for a second time interval.

Abstract: The present disclosure provides a controller for controlling a GaN-based semiconductor device. The controller is configured to receive a current sensing signal VCS which is indicative of a drain-to-source current of the GaN-based semiconductor device and generate a control driving signal VDRV to the GaN-based semiconductor device such that a gate-to-source voltage VGS applied to the GaN-based semiconductor device for switching on the GaN-based semiconductor device is stabilized to a voltage value equal to a reference voltage Vref over an on-time duration. Impact of the change in the voltage drop across the current sensing resistor to the operation of the GaN-based semiconductor device is eliminated.

Abstract: The subject application provides a zero-voltage switching flyback converter comprising: a transformer having a primary winding and a secondary winding; a primary switch and a secondary switch for conducting the currents flowing in the primary winding and secondary winding respectively. A timing control method for operating the flyback converter are provided to accomplish zero-voltage switch by turning on the secondary switch twice within one switching power cycle.

Abstract: The subject application provides a zero-voltage switching flyback converter comprising: a transformer having a primary winding and a secondary winding; a primary switch and a secondary switch for conducting the currents flowing in the primary winding and secondary winding respectively. A timing control method for operating the flyback converter are provided to accomplish zero-voltage switch by turning on the secondary switch twice within one switching power cycle.