Abstract: A method and system for processing graphics in tile-based rendering mode are disclosed. The system includes: a geometry processing system configured to perform geometry processing on primitives to tile visible primitives into a plurality of tiles M in screen view space; and a fragment processing system configured to render the plurality of tiles M and generate rendered images of the plurality of tiles M, where the fragment processing system includes a post-processing module configured to: start to perform pixel filtering on pixels in a first pixel set Pin0 of a target tile M0 in the plurality of tiles M at a first time after a rendered image of the target tile M0 is generated and before all the rendered images of the plurality of tiles M are generated. The present disclosure can effectively improve processing efficiency of overall image pixel filtering, without generating additional pixel shading workload.

Abstract: The present disclosure discloses a high-bandwidth double data rate (DDR) dual-in-line memory module (DIMM), a memory system, and an operation method of the memory system.

Abstract: A double data rate dual-in-line memory module (DDR DIMM), a memory system and an operation method thereof using a data buffer for error correction are disclosed. In an example, the DDR DIMM includes a first channel including a first group of DRAM chips and a first data buffer corresponding to the first group of DRAM chips; wherein: the first data buffer is configured to obtain all write data signals input to the first channel, encode write data of all the write data signals to generate a first ECC, and send the first ECC and the write data to the first group of DRAM chips in a write operation. The disclosure can realize excellent error detection and error correction within the memory module and can greatly reduce bit error rate of the entire memory module.

Abstract: A method and system for processing graphics in tile-based rendering mode are disclosed. The system includes: a geometry processing system configured to perform geometry processing on primitives to tile visible primitives into a plurality of tiles M in screen view space; and a fragment processing system configured to render the plurality of tiles M to generate rendered images of the plurality of tiles M. The fragment processing system includes a post-processing module configured to start to perform pixel filtering on pixels in a first pixel set Pin0 of a target tile M0 in the plurality of tiles M at a first time after a rendered image of the target tile M0 is generated and before all the rendered images of the plurality of tiles M are generated. The present disclosure can effectively improve processing efficiency of overall image pixel filtering, without generating additional pixel shading workload.

Abstract: A method and system for processing graphics in tile-based rendering mode are disclosed. The system includes: a geometry processing system configured to perform geometry processing on primitives to tile visible primitives into a plurality of tiles M in screen view space; and a fragment processing system configured to render the plurality of tiles M and generate rendered images of the plurality of tiles M, where the fragment processing system includes a post-processing module configured to: start to perform pixel filtering on pixels in a first pixel set Pin0 of a target tile M0 in the plurality of tiles M at a first time after a rendered image of the target tile M0 is generated and before all the rendered images of the plurality of tiles M are generated. The present disclosure can effectively improve processing efficiency of overall image pixel filtering, without generating additional pixel shading workload.

Abstract: The present disclosure discloses a method and system for processing graphics in tile-based rendering mode by expanding boundaries of tiles. The system includes: a geometry processing system configured to perform geometry processing on primitives to tile visible primitives into a plurality of expanded tiles M? in screen view space; and a fragment processing system configured to render each expanded tile M? to obtain rendered images of the plurality of expanded tiles M?, and enable a filter kernel to perform pixel filtering according to the rendered image of each expanded tile M?, where the plurality of expanded tiles M? are obtained by dividing the screen view space into a plurality of tiles M and expanding boundaries of the plurality of tiles M respectively. In the present disclosure, the pixel filtering process can be done after rendering of each tile, thereby effectively improving the processing efficiency of pixel filtering.

Abstract: A graphics processing method and system are disclosed. The system includes multiple cores with a master mode core and at least one slave mode core, where the master mode core is configured to construct primitives according to input geometry data, split the constructed primitives into primitive core groups, and distribute the primitive core groups to the master mode core and the at least one slave mode core; and the master mode core and the at least one slave mode core are configured to process the distributed primitive core groups to obtain a rendered image. The system and method of the present disclosure provide powerful parallel data processing capability, which allows for processing of a massive amount of geometry data, and enable excellent performance by taking actual working states of hardware into full consideration.

Abstract: The present disclosure discloses a high-bandwidth double data rate (DDR) dual-in-line memory module (DIMM), a memory system, and an operation method of the memory system.

Abstract: A double data rate dual-in-line memory module (DDR DIMM), a memory system and an operation method thereof using a data buffer for error correction are disclosed. In an example, the DDR DIMM includes a first channel including a first group of DRAM chips and a first data buffer corresponding to the first group of DRAM chips; wherein: the first data buffer is configured to obtain all write data signals input to the first channel, encode write data of all the write data signals to generate a first ECC, and send the first ECC and the write data to the first group of DRAM chips in a write operation. The disclosure can realize excellent error detection and error correction within the memory module and can greatly reduce bit error rate of the entire memory module.