Abstract: Frame injection apparatus for injecting frames from a host device into a switched Ethernet network comprises a frame memory operable to receive and store one host frame at a time and to inject the frame onto the Ethernet switched network between network frames and to buffer network frames received during the time that the host frame is being injected onto the network.

Abstract: A packet data network traffic management device comprises a plurality of ports comprising at least a first port, a second port, and a third port; and a plurality of deterministic multi-threaded deterministic micro-controllers, each of the micro-controllers associated with a corresponding one of the ports to control packet data through the corresponding port; and the plurality of multi-threaded deterministic micro-controllers cooperatively operate to selectively communicate data packets between the plurality of ports.

Abstract: A method is provided for operating a communication controller coupling a device comprising a processor with a bus. The method comprises: receiving a plurality of types of data packets via the bus and processing received data packets before making available said received data packets to the device processor. The processing of received data packets comprises: evaluating each received data packet in accordance with predetermined criteria; rejecting any of the received data packets that fails to meet the predetermined criteria; identifying non-rejected data packets having high priority; identifying said non-rejected other data packets having lower priority; providing a high priority data path to the processor for the high priority data packets; providing at least one additional data path to the processor for the other data packets; and providing a high priority alert to the device processor to the presence of high priority data packets at the high priority channel.

Abstract: A packet data network traffic management device comprises a plurality of ports comprising at least a first port, a second port, and a third port; and a plurality of deterministic multi-threaded deterministic micro-controllers, each of the micro-controllers associated with a corresponding one of the ports to control packet data through the corresponding port; and the plurality of multi-threaded deterministic micro-controllers cooperatively operate to selectively communicate data packets between the plurality of ports.

Abstract: An Ethernet interface module comprises a first full duplex port, a second duplex port, a first path coupling the first duplex port and the second full duplex port, a second path coupling the second full duplex port and the first full duplex port, a first queue disposed in the first path, a second queue disposed in the second path, a third path comprising at least a portion of the first queue coupling the receive and transmit portions of the first port, a fourth path comprising at least a portion of the second queue coupling the receive and transmit portions of the second port, execution apparatus operable responsive to a command to alter the state of said Ethernet interface module, or the contents of said received frame to produce a return frame comprising fields of a received frame that are modified, or both.

Abstract: A packet data network traffic management device comprises a plurality of ports comprising at least a first port, a second port, and a third port; and a plurality of deterministic multi-threaded deterministic micro-controllers, each of the micro-controllers associated with a corresponding one of the ports to control packet data through the corresponding port; and the plurality of multi-threaded deterministic micro-controllers cooperatively operate to selectively communicate data packets between the plurality of ports.

Abstract: An improved Ethernet traffic management device is provided comprising. a first port, a second port, and a third port. The device further comprises a first deterministic multi-threaded micro-controller controlling traffic through the first port, a second deterministic multi-threaded micro-controller controlling traffic through the second port, and a third deterministic multi-threaded micro-controller controlling traffic through the third port. The first deterministic multi-threaded micro-controller, second deterministic multi-threaded micro-controller, and third deterministic multi-threaded micro-controller cooperatively operate to selectively communicate data packets between each of the first, second and third ports.

Abstract: An Ethernet interface module comprises a duplex port operable to transfer frames between said Ethernet network and a device and a path coupling a receive portion of the duplex port to a transmit portion of said first full duplex port. A queue is disposed in said first path. Evaluation apparatus is coupled to the queue and determines whether a received frame is addressed to said Ethernet interface module and whether a frame type field contains a frame type. The Ethernet interface module is operable in a first mode such that every said received frame is echoed back out the full duplex port; and is operable in a second mode such that each received frame that meets predetermined evaluation criteria is echoed back out the duplex port and those received frames that do not meet the predetermined evaluation criteria are discarded.

Abstract: An Ethernet interface comprises a first full duplex port and a second duplex port each operable to transfer frames between a network and a device. The Ethernet interface module further comprises a first path coupling the first duplex port and the second full duplex port; a second path coupling the second full duplex port and the first full duplex port; a first queue disposed in the first path; a second queue disposed in the second path; and evaluation apparatus coupled to the first queue and to the second queue.

Abstract: A method and apparatus are disclosed to provide ad-hoc synchronization in industrial networks between a programmable logic controller and each I/O device without any specific protocol extensions or distributed clock scheme. An embodiment of an industrial control network comprising a Programmable Logic Controller (PLC), a network coupled to the PLC, and a plurality of networked input/output (I/O) devices coupled to the network is provided. Each I/O device comprises: inputs coupled to the network to receive data from the PLC as device input data; and outputs coupled to the network to transmit output data from the I/O device to the PLC. The embodiment further comprises a programmable timer initiating an I/O cycle for the device on a periodic basis. The I/O device is operable to determine a first time period starting at the time at which specific output data arrives from the PLC and ending when the period of the timer ends. The first time period is compared to a predetermined time period.

Abstract: An Ethernet interface module comprises a first full duplex port, a second duplex port, a first path coupling the first duplex port and the second full duplex port, a second path coupling the second full duplex port and the first full duplex port, a first queue disposed in the first path, a second queue disposed in the second path, a third path comprising at least a portion of the first queue coupling the receive and transmit portions of the first port, a fourth path comprising at least a portion of the second queue coupling the receive and transmit portions of the second port, execution apparatus operable responsive to a command to alter the state of said Ethernet interface module, or the contents of said received frame to produce a return frame comprising fields of a received frame that are modified, or both.

Abstract: An Ethernet interface module comprises a duplex port operable to transfer frames between said Ethernet network and a device and a path coupling a receive portion of the duplex port to a transmit portion of said first full duplex port. A queue is disposed in said first path. Evaluation apparatus is coupled to the queue and determines whether a received frame is addressed to said Ethernet interface module and whether a frame type field contains a frame type. The Ethernet interface module is operable in a first mode such that every said received frame is echoed back out the full duplex port; and is operable in a second mode such that each received frame that meets predetermined evaluation criteria is echoed back out the duplex port and those received frames that do not meet the predetermined evaluation criteria are discarded.

Abstract: A communication controller apparatus couples a device comprising a device processor to a data bus. The communication controller comprises an input/output controller coupled to the bus to receive a plurality of types of data packets. The types of data packets comprise at least one type of data packets having a high priority determined by timing criticality. The input/output controller is operable to process data packets received via the bus before providing any of the received data packets to the device processor. The communication controller comprises a high priority data path comprising a high priority data packet queue a low priority data path to the device comprising a low priority data packet queue.

Abstract: An Ethernet interface comprises a first full duplex port and a second duplex port each operable to transfer frames between a network and a device. The Ethernet interface module further comprises a first path coupling the first duplex port and the second full duplex port; a second path coupling the second full duplex port and the first full duplex port; a first queue disposed in the first path; a second queue disposed in the second path; and evaluation apparatus coupled to the first queue and to the second queue.

Abstract: A method is provided for operating a communication controller coupling a device comprising a processor with a bus. The method comprises: receiving a plurality of types of data packets via the bus and processing received data packets before making available said received data packets to the device processor. The processing of received data packets comprises: evaluating each received data packet in accordance with predetermined criteria; rejecting any of the received data packets that fails to meet the predetermined criteria; identifying non-rejected data packets having high priority; identifying said non-rejected other data packets having lower priority; providing a high priority data path to the processor for the high priority data packets; providing at least one additional data path to the processor for the other data packets; and providing a high priority alert to the device processor to the presence of high priority data packets at the high priority channel.

Abstract: A method for preventing priority inversion in a processor system having an operating system operable in a plurality of contexts is provided. The method comprises: providing a plurality of context control registers with each context control register being associated with a corresponding one context for controlling execution of the context; providing a plurality of sets of hardware registers, each set corresponding to one context of the plurality of contexts; and utilizing the plurality of context control registers and said plurality of sets of hardware registers to prevent priority inversion.

Abstract: A configurable application specific product with a configurable input/output interface is described. The illustrative embodiment of the invention includes a single microcontroller and a microprocessor having a configurable I/O interface that can be programmed to handle any one of a plurality of interfaces that embedded applications might have, including communication protocols and bus interfaces, data acquisition from multiple sensors and actuators, and controls of various motors.

Abstract: A trace function method for microprocessors is provided. The method is operable with a microprocessor comprising an execution unit operable in one or a plurality of contexts. The method comprises: providing a memory coupled to the execution unit, utilizing the memory to store trace data during a trace operation; and providing hardware utilizable during a trace operation to assist in the trace operation.

Abstract: A deterministic microprocessor is disclosed in which a plurality of sets of hardware registers is provided. A corresponding plurality of hardware contexts for the microcontroller is provided by the plurality of sets of hardware registers. A context manager controls the selection of the hardware registers such that contexts are changed within one bus cycle and a plurality of hardware contexts are provided.

Abstract: A configurable input/output interface is described that can be programmed to handle any one of a plurality of interfaces that embedded applications might have, including communication protocols and bus interfaces, data acquisition from multiple sensors and actuators, and controls of various motors.