Patents Assigned to Innovations In Memory LLC
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Publication number: 20250053479Abstract: A memory controller is configured to receive segment pointers that identify physical memory devices and slices for associated segments. The memory controller is configured to identify a most-full first one of the physical memory devices, to identify a most-empty second one of the physical memory devices, and to identify one of the segments in the most-full first one of the physical memory devices. The memory controller is configured to move a slice from the identified one of the segments in the most-full first one of the physical memory devices to the most-empty second one of the physical memory devices. The memory controller is configured to update one of the segment pointers for the identified segment. The memory controller is configured to update one of the segment pointers for the identified segment by removing a previous segment pointer to the most-full first one of the physical memory devices.Type: ApplicationFiled: October 30, 2024Publication date: February 13, 2025Applicant: Innovations In Memory LLC.Inventors: Timothy STOAKES, Mark LEWIS
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Patent number: 12158811Abstract: A method implemented by a memory controller may comprise receiving segment pointers that identify memory devices and slices for associated segments. The method may comprise identifying a most-full first one of the memory devices. The method may comprise identifying a most-empty second one of the memory devices. The method may comprise identifying one of the segments in the most-full one of the memory devices. The method may comprise moving a slice from the identified one of the segments in the most-full one of the memory devices to the most-empty one of the memory devices. The method may comprise updating one of the segment pointers for the identified segment.Type: GrantFiled: February 17, 2023Date of Patent: December 3, 2024Assignee: Innovations in Memory LLCInventors: Timothy Stoakes, Mark Lewis
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Publication number: 20240302983Abstract: A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.Type: ApplicationFiled: March 18, 2024Publication date: September 12, 2024Applicant: Innovations In Memory LLCInventor: Jon C.R. Bennett
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Publication number: 20240264742Abstract: A method of managing a memory system is described, the memory system having a processor with a client interface, a buffer memory, and a storage memory. A LUN (logical unit) is exposed to the client, the LUN having a memory size, and QoS specification. When the processor receives a command from the client to write data to the LUN, determining if the QoS specification includes deduplication and: if the QoS does not include deduplication, processing the command by storing the data in the storage memory and creating metadata uniquely referencing a storage location of the data that is written; or if the QoS includes deduplication, determine if deduplication is possible while meeting a latency value as specified in the QoS specification and performing deduplication.Type: ApplicationFiled: December 26, 2023Publication date: August 8, 2024Applicant: Innovations In Memory LLCInventors: Amit Garg, Timothy Stoakes, Vikas Ratna
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Patent number: 11960743Abstract: A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.Type: GrantFiled: March 6, 2023Date of Patent: April 16, 2024Assignee: INNOVATIONS IN MEMORY LLCInventor: Jon C. R. Bennett
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Patent number: 11886704Abstract: A method of managing a memory system is described, the memory system having a processor with a client interface, a buffer memory, and a storage memory. A LUN (logical unit) is exposed to the client, the LUN having a memory size, and QoS specification. When the processor receives a command from the client to write data to the LUN, determining if the QoS specification includes deduplication and: if the QoS does not include deduplication, processing the command by storing the data in the storage memory and creating metadata uniquely referencing a storage location of the data that is written; or if the QoS includes deduplication, determine if deduplication is possible while meeting a latency value as specified in the QoS specification and performing deduplication.Type: GrantFiled: August 9, 2021Date of Patent: January 30, 2024Assignee: Innovations In Memory LLCInventors: Amit Garg, Timothy Stoakes, Vikas Ratna
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Publication number: 20230280920Abstract: A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.Type: ApplicationFiled: March 6, 2023Publication date: September 7, 2023Applicant: Innovations In Memory LLCInventor: Jon C.R. Bennett
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Publication number: 20230281079Abstract: A method implemented by a memory controller may comprise receiving segment pointers that identify memory devices and slices for associated segments. The method may comprise identifying a most-full first one of the memory devices. The method may comprise identifying a most-empty second one of the memory devices. The method may comprise identifying one of the segments in the most-full one of the memory devices. The method may comprise moving a slice from the identified one of the segments in the most-full one of the memory devices to the most-empty one of the memory devices. The method may comprise updating one of the segment pointers for the identified segment.Type: ApplicationFiled: February 17, 2023Publication date: September 7, 2023Applicant: Innovations in Memory LLCInventors: Timothy STOAKES, Mark Lewis
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Patent number: 11599285Abstract: A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.Type: GrantFiled: May 14, 2021Date of Patent: March 7, 2023Assignee: Innovations In Memory LLCInventor: Jon C. R. Bennett
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Patent number: 11586501Abstract: A memory system uses a dynamic RAID scheme to dynamically encode RAID address space geometries. The dynamic RAID scheme solves issues with the algorithmic layout approach and flat virtual address space used in conventional RAID systems. The dynamic RAID scheme can be used for any RAID algorithm and does not require static mapping. In other words, there is no requirement that each strip be located in the same relative location in memory devices and there is no requirement that stripes use the same combination of memory devices.Type: GrantFiled: May 14, 2021Date of Patent: February 21, 2023Assignee: Innovations In Memory LLCInventors: Timothy Stoakes, Mark Lewis
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Publication number: 20220035529Abstract: A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.Type: ApplicationFiled: May 14, 2021Publication date: February 3, 2022Applicant: Innovations In Memory LLCInventor: Jon C.R. BENNETT
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Publication number: 20220027075Abstract: A method of managing a memory system is described, the memory system having a processor with a client interface, a buffer memory, and a storage memory. A LUN (logical unit) is exposed to the client, the LUN having a memory size, and QoS specification. When the processor receives a command from the client to write data to the LUN, determining if the QoS specification includes deduplication and: if the QoS does not include deduplication, processing the command by storing the data in the storage memory and creating metadata uniquely referencing a storage location of the data that is written; or if the QoS includes deduplication, determine if deduplication is possible while meeting a latency value as specified in the QoS specification and performing deduplication.Type: ApplicationFiled: August 9, 2021Publication date: January 27, 2022Applicant: Innovations In Memory LLCInventors: Amit Garg, Timothy Stoakes, Vikas Ratna
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Patent number: RE49998Abstract: A storage system and method of operating the storage system is described where the metadata used to access the data stored in a storage device is distributed amongst a plurality of controllers in communication with a user, with each other and with the storage device. Each controller stores at least the metadata needed to access the data relevant to the user at the time, and metadata is updated to respond to internal system activities such as device failures, snapshots, backup operations or the like. To preserve coherence of the metadata, each metadata update is communicated to the other controllers and the storage device. The update is either transmitted to the other controllers and to the storage device and each metadata location is updated, or the update is transmitted to the storage device and each of the controllers is instructed to request an update from the storage device.Type: GrantFiled: September 17, 2021Date of Patent: June 4, 2024Assignee: Innovations in Memory LLCInventors: Jagadish Kumar Mukku, Hector Cuellar
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Patent number: RE50315Abstract: Data being stored in a block of flash memory system may be characterized as being frequently modified or infrequently modified (hot/cold) based on a heuristic. When performing garbage collection, if the data from hot blocks is consolidated and data from cold blocks is separately consolidated by writing the data to different free blocks, the number of write operations to perform the garbage collection may be reduced. The lower “write amplification” contributes to increasing the lifetime of the memory circuit. When the number of blocks in a pool of previously erased blocks is reduced to a threshold value, a block having data previously stored therein may be selected for garbage collection based on a second heuristic.Type: GrantFiled: September 10, 2021Date of Patent: February 25, 2025Assignee: INNOVATIONS IN MEMORY LLCInventor: Silei Zhang