Abstract: The invention provides an apparatus and method for reducing the access time of a memory cell after a write operation. A one-shot generation circuit generates a one-shot pulse in response to a falling edge on an external write line or a change in the state of the data signal during an inactive state of the write signal. This one-shot pulse then controls writing data into a static memory cell. Since it is not necessary to wait for the write external line to go high before triggering the end of the internal write pulse, the access time of the static memory device is reduced.

Abstract: Wafer level integration is provided by using individually integrated circuits on a wafer substrate and generating an electrically ordered matrix of functional integrated circuits assigned from a random distribution of functional, partially functional, and non-functional circuits. Each circuit is individually tested for functionality and thereafter a conductive grid is formed on said wafer to interconnect all of the circuits on the wafer. Circuits that are tested as being non-functional are isolated prior to formation of the interconnecting grid by eliminating fuses that provide connections between the defective circuit and the conductive grid. Each matrix row includes redundant decoder lines. The redundant decoder lines are programmed to reassign functional circuits from a semiconductor wafer substrate location to a matrix row location in another matrix row having defective circuits. In this way, complete functional matrix rows are formed.