Abstract: A method for operating a secure semiconductor IP access server to support failure analysis. A client presents a test failure and failure type to an automated server which traverses an electronic product design, definition, and test database to report specifically those components and interconnect likely to cause the failure with geometrical information which may be displayed on the client. Other aspects of semiconductor IP are protected by the server by limiting the trace mechanism and renaming components.

Abstract: A process for identifying the location of a break in a scan chain in real time as fail data is collected from a tester. Processing a test pattern before applying it on a tester provides a signature enabling a method for a tester to identify a scan cell which is stuck during the time the tester is operating on a device under test rather than accumulating voluminous test data sets for delayed offline analysis.

Abstract: A failure mask memory is added to a semiconductor tester. In conjunction with a new failure filter, failures may be ignored or used to update the contents of failure mask memory. Only the first instance of a failure is reported reducing the size of test data logs.

Abstract: A method for determining that failures in semiconductor test are due to a defect potentially causing a hold time violation in a scan cell in a scan chain, counting the number of potential defects, and, if possible, localizing, and ameliorating hold time defects in a scan chain.

Abstract: An apparatus for locating a defect in a scan chain by recording the last bit position in a serial data stream at which a certain data state is observed during a test comprising a plurality of patterns.

Abstract: A process for identifying the location of a break in a scan chain in real time as fail data is collected from a tester. Processing a test pattern before applying it on a tester provides a signature enabling a method for a tester to identify a scan cell which is stuck during the time the tester is operating on a device under test rather than accumulating voluminous test data sets for delayed offline analysis.

Abstract: A method for data logging from inside a semiconductor device, yielding timing performance information about the logic behind each and every flip-flop in the scan chain and displaying the sensitivity of certain flipflops to speed related manufacturing defects. The method comprises steps for testing, measuring, storing, and analyzing records for frequency characterization of complex digital semiconductors.

Abstract: A process for conserving storage space and time while recording not only a pass or fail result per die but also additional failure test pattern data by computing and comparing digital fault signatures or hash values on a tester.

Abstract: A process for improving design-limited yield by collecting test fail data, converting to electrical faults, and localizing to physical area on semiconductor die. The steps of identifying an area on a wafer containing a fault to enable the analysis of specific defects, accumulating data suitable for yield monitoring analysis based on pattern test failures logged on scan cells in scan chains on automatic test equipment, and translating scan cell and scan chain failure reports to geometric locations of electrical structures on wafers.

Abstract: A digitally controlled hybrid power module is controlled by a programmable controller. The hybrid power module includes a digitally controlled switching supply with an output coupled to an input of a digitally controlled linear voltage regulator. Independent control of switching supply and the linear regulator is provided by the programmable controller, which may be a field programmable gate array (FPGA), microcontroller, or digital signal processor (DSP). The programmable controller may independently control one or more power modules. Each power module may also include enable switching and an associated current clamp for capacitive loads. An output voltage transient suppressor may also be used to control transients, such as those produced under fast switching conditions.

Abstract: A programmable time event and waveform generator for the application of precise timing patterns to a logic circuit and the capture of response data from the logic circuit. The time event and waveform generator comprises a programmable delay element that is programmed with values stored in pattern memory. For scan based testing, the time event and waveform generator is programmed between test pattern scan sequences by serial loading from the test pattern memory. The generator may be used to generate precise signal transitions to input pins of a circuit under test, and to capture at precise times the signal states from the output pins of a circuit under test. The data for programming the delay element is accessed from test pattern memory.

Abstract: A method and system for automated multisite testing. Specifically, in one embodiment, a method is disclosed for determining a testing order of plurality of testing operations of a test flow in a multisite testing environment. The method begins by automatically walking through the test flow by performing recursion on the plurality of testing operations. Next, the method automatically assigns a plurality of relative priorities to the plurality of testing operations. The plurality of relative priorities determine the testing order used when executing each of the plurality of testing operations in said test flow. Each of the plurality of testing operations is executed only once when testing a plurality of devices under test (DUTs) in the multisite testing environment.

Abstract: A single memory automated test equipment (ATE) system having multiple pin segments with dynamic pin reallocation. Each pin segment having a length 2n is coupled to the single memory by a parallel in/parallel out shift register that also has a length 2n. The single memory is used to store both parallel data vectors and serial data vectors. Each output of the shift register is coupled to one pin of the corresponding pin segment. Selected, e.g., every other output of the shift register is also coupled to a data selection circuit associated with each pin of the pin segment. The contents of the shift register may be divided into a number of equal length serial data streams. The data selection circuit provides for coupling any serial data stream from the shift register to any pin within the pin segment, and for coupling a single serial data stream to more than one pin.

Abstract: A programmable time event and waveform generator for the application of precise timing patterns to a logic circuit and the capture of response data from the logic circuit. The time event and waveform generator comprises a programmable delay element that is programmed with values stored in pattern memory. For scan based testing, the time event and waveform generator is programmed between test pattern scan sequences by serial loading from the test pattern memory. The generator may be used to generate precise signal transitions to input pins of a circuit under test, and to capture at precise times the signal states from the output pins of a circuit under test. The data for programming the delay element is accessed from test pattern memory.

Abstract: An invention is disclosed which automates the discovery in a digital logic semiconductor device of the location of a defect which causes signals to propagate in a manner delayed from the defect free condition. A tester operating system controls application of test patterns designed for delay fault discovery and causes a static timing verifier application to choose additional paths to test which in combination, elucidate the location to one segment of the problematical path.

Abstract: The present invention is a circuit for controlling current. In one embodiment, the high reference voltage input of a digital to analog converter is coupled with a reference voltage source which provides a positive reference voltage. A resistive load is coupled to an output of the digital to analog converter and to a circuit output pin. A sensing device couples the circuit output pin with the low reference voltage input of the digital to analog converter and to a reference ground input of the voltage source. The positive reference voltage, low reference voltage, and reference ground voltage are changed in response to the sensing device detecting a change in the output voltage.

Abstract: An SRAM efficient ATE system that performs high speed nested loops without constraints on loop size or modularity and that loops and/or branches from any vector in a multiple vector accessed word to any vector in another multiple vector accessed word without incurring any time displacement. In one embodiment, the maximum required vector rate is less than or equal the average sustained data rate of the SDRAM and is less than or equal to the maximum access rate of the dual port SRAM's memory B. The output of the SDRAM's memory A consists of one control word and one vector (nV=1). The I/O port widths of the SRAM's memory B are the same. In another embodiment, the maximum required vector rate is greater than the average sustained data rate of the SDRAM's memory A, but is equal to or less than the maximum access rate of the SRAM's memory B. The output of the SDRAM's memory A consists of multiple control words and vectors. The input port of the SRAM's memory B is some multiple of the output port width.

Abstract: The present invention is a circuit for controlling current. In one embodiment, the high reference voltage input of a digital to analog converter is coupled with a reference voltage source which provides a positive reference voltage. A resistive load is coupled to an output of the digital to analog converter and to a circuit output pin. A sensing device couples the circuit output pin with the low reference voltage input of the digital to analog converter and to a reference ground input of the voltage source. The positive reference voltage, low reference voltage, and reference ground voltage are changed in response to the sensing device detecting a change in the output voltage.

Abstract: An SRAM efficient ATE system that performs high speed nested loops without constraints on loop size or modularity and that loops and/or branches from any vector in a multiple vector accessed word to any vector in another multiple vector accessed word without incurring any time displacement. In one embodiment, the maximum required vector rate is less than or equal the average sustained data rate of the SDRAM and is less than or equal to the maximum access rate of the dual port SRAM's memory B. The output of the SDRAM's memory A consists of one control word and one vector (nV=1). The I/O port widths of the SRAM's memory B are the same. In another embodiment, the maximum required vector rate is greater than the average sustained data rate of the SDRAM's memory A, but is equal to or less than the maximum access rate of the SRAM's memory B. The output of the SDRAM's memory A consists of multiple control words and vectors.