Abstract: A remote mapping method, apparatus and device for computing resources, and a storage medium, which are applied to a server. Said method comprises: identifying each FPGA heterogeneous accelerator card in an FPGA BOX; establishing a network communication connection with each FPGA heterogeneous accelerator card via a network interface of each FPGA heterogeneous accelerator card in the FPGA BOX, and establishing a network communication connection between FPGA heterogeneous accelerator cards; mapping each FPGA heterogeneous accelerator card to the server; establishing network transmission for the established network communication connections, and migrating a control flow and a data flow that are performed by the PCIE to the network transmission; and deploying a target application in the FPGA BOX through the established network transmission, and when running the target application, performing data exchange with the FPGA BOX via the network transmission.

Abstract: An image processing method, apparatus and device, and a readable storage medium are disclosed, including: obtaining a target image; inputting the target image into a quantized target deep neural network model for classification/detection to obtain an output result; and processing the target image according to a policy corresponding to the output result. A process of performing quantization to obtain the target deep neural network model includes: obtaining a pre-trained floating point type deep neural network model; extracting weight features of a deep neural network model; determining a quantization policy using the weight features; and quantizing the deep neural network model according to the quantization policy to obtain the target deep neural network model.

Abstract: A clock control method, apparatus, and device, and a storage medium. By the method, timing optimization of bidirectional data communication between a server mainboard and a Peripheral Component Interconnect express (PCIe) expansion board is relatively implemented, and the occurrence of a situation where in any data communication direction between the server mainboard and the PCIe expansion board, data transmitted by the initiating end at a given high-level moment does not reach the receiving end at a next high-level moment may be prevented, thus ensuring the reliability of communication between the server mainboard and the PCIe expansion board. In addition, the present application further provides a clock control apparatus and device, and a storage medium, and the beneficial effects are as stated above.

Abstract: An I2C bus communication control method, device and system, and a readable storage medium. The method comprises: receiving configuration information of an I2C bus sent by an upper-layer application; analyzing the configuration information to obtain a plurality of polling parameters; writing the plurality of polling parameters into a polling table; and controlling the I2C bus, and executing a corresponding read-write operation according to the polling table. In the method, the read-write operation executed on the I2C bus is performed according to the polling table, thus an accurate communication condition of the I2C bus can be directly obtained on the basis of the polling table without accessing a bus state in a polling manner; congestion risks can be reduced, and the access efficiency of a single main device can also be achieved when a plurality of main devices exist.

Abstract: An instruction execution method, apparatus and device, and a storage medium are provided. According to the method, normal execution of the instructions without an execution dependency relationship in the batch processing process is ensured, and meanwhile, ordered execution of the instructions with the execution dependency relationship is ensured, and then the correctness of instruction execution results is ensured. In addition, the present application further provides an instruction execution apparatus and device and a storage medium, and the beneficial effects are the same as described above.

Abstract: A hybrid heterogeneous host system, a resource configuration method and a task scheduling method are disclosed. The system includes: a basic unit, including: computing resource nodes, storage resource nodes and input/output I/O resource nodes; wherein multiple basic units are connected via a high-speed internetwork; and a software definition unit, configured to: when system resources are increased or reduced, extend the address space of an increased hardware resource to a current address space, or delete an address space of a reduced hardware resource from the current address space, and update a system resource view. Through the embodiments of the present invention, the extendibility of a tightly coupled shared memory system can be guaranteed, and the design complexity and cost of the multiway system also can be greatly reduced, which improves the flexibility and reusability of the system.

Abstract: A method and system for implementing a directory structure of a host system are disclosed. The method includes: multiple basic computing units interconnecting via a high speed internetwork to construct a system computing unit set; wherein each basic computing unit comprises a protocol processing chip and a system resource management firmware; and dividing a part implementing a logic function in the protocol processing chip into a static part and a dynamic part in advance, wherein the dynamic part can be reconstructed; constructing a system cache directory storage architecture through the dynamic part; and the system resource management firmware managing system resources by means of configuration.

Abstract: A prototype verification system and method are provided for a high-end fault-tolerant computer. The system includes multiple single junction prototype verification systems and an interconnection router chipset. The single junction prototype verification systems are interconnected through the interconnection router chipset. Each single junction prototype verification system includes a computer board which is a four-path tightly-coupled computer board, and a chip verification board including two junction controller chipsets. Each junction controller chipset includes two field-programmable gate array (FGPA) chips which bear a logic of one junction controller together, and an interconnection board including two FGPA chips. Each FPGA chip provides a high speed interconnection port used to achieve protocol interconnection between two paths of the computer board and one of the junction controller chipsets.

Abstract: The present invention provides a high-end fault-tolerant computer system and an implementation method. The system includes N single junction prototype verification systems and M crossbar-switch interconnection router chipsets. Each crossbar-switch interconnection router chipset is used to achieve the interconnection among the N single junction prototype verification systems. Switching is not performed among all crossbar-switch interconnection router chipsets, and both M and N are positive integers greater than or equal to 2. The single junction includes: a computer board, which is 4-path tightly-coupled computer board, and a junction controller for controlling 2 paths of CPUs on the computer board. The present invention can effectively realize the global memories sharing, balance the system transmission bandwidth and delay, and solve the problem of the integration reliability of multi-path CPU system.

Abstract: A prototype verification system and method are provided for a high-end fault-tolerant computer. The system includes multiple single junction prototype verification systems and an interconnection router chipset. The single junction prototype verification systems are interconnected through the interconnection router chipset. Each single junction prototype verification system includes a computer board which is a four-path tightly-coupled computer board, and a chip verification board including two junction controller chipsets. Each junction controller chipset includes two field-programmable gate array (FGPA) chips which bear a logic of one junction controller together, and an interconnection board including two FGPA chips. Each FPGA chip provides a high speed interconnection port used to achieve protocol interconnection between two paths of the computer board and one of the junction controller chipsets.