Abstract: A method of converting a Boolean logic circuit into an asynchronous multi-rail circuit is provided. A Boolean logic circuit is converted into a first multi-rail circuit using at least Shannon's expansion. The first multi-rail circuit is technology mapped into a second multi-rail circuit. Completion detection circuitry is added which receives the primary outputs of the second multi-rail circuit.
Type:
Grant
Filed:
October 25, 2007
Date of Patent:
January 11, 2011
Assignee:
Institute of Computer Science, Foundation for Research and Technology- Hellas
Inventors:
Christos P. Sotiriou, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno
Abstract: According to an embodiment of the invention, a system for identifying when a running speed of an integrated circuit is within an applied clock speed is provided. A monotonic circuit is configured to receive input data and transmit output data. A completion detection circuit is configured to generate a completion detection signal for the monotonic circuit. A comparator is configured to compare at least the completion detection signal and a clock signal, and configured to emit an error signal if the clock signal arrives before the completion detection signal. A synchronous circuit element is configured to receive at least a portion of the output data and configured to be clock driven by the clock signal. The error signal represents that the clock speed is faster than an operating speed of the monotonic circuit.
Type:
Grant
Filed:
January 12, 2006
Date of Patent:
December 28, 2010
Assignee:
Institute of Computer Science, Foundation for Research and Technology-Hellas
Abstract: According to one embodiment of the present invention, a system for identifying a running speed of an integrated circuit is provided. An asynchronous multi-rail circuit is configured to receive input data and transmit output data. A completion detection circuit is configured to generate a completion detection signal for the asynchronous multi-rail circuit. A variable clock generator configured to be driven by at least the completion detection signal. A synchronous circuit element configured to receive at least a portion of the output data and configured to be clock driven by a clock signal from the variable clock generator. A period of the clock signal represents a running speed of the asynchronous circuit.
Type:
Grant
Filed:
December 17, 2007
Date of Patent:
May 4, 2010
Assignee:
Institute of Computer Science, Foundation for Research and Technology -Hellas
Abstract: A method of converting a Boolean logic circuit into an asynchronous multi-rail circuit is provided. A Boolean logic circuit is converted into a first multi-rail circuit using at least Shannon's expansion. The first multi-rail circuit is technology mapped into a second multi-rail circuit. Completion detection circuitry is added which receives the primary outputs of the second multi-rail circuit.
Type:
Application
Filed:
October 25, 2007
Publication date:
July 16, 2009
Applicant:
Institute of Computer Science, Foundation for Research and Technology - Hellas ("ICS")
Inventors:
Christos P. Sotiriou, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno
Abstract: According to one embodiment of the present invention, a system for identifying a running speed of an integrated circuit is provided. An asynchronous multi-rail circuit is configured to receive input data and transmit output data. A completion detection circuit is configured to generate a completion detection signal for the asynchronous multi-rail circuit. A variable clock generator configured to be driven by at least the completion detection signal. A synchronous circuit element configured to receive at least a portion of the output data and configured to be clock driven by a clock signal from the variable clock generator. A period of the clock signal represents a running speed of the asynchronous circuit.
Type:
Grant
Filed:
December 23, 2005
Date of Patent:
January 8, 2008
Assignee:
Institute of Computer Science, Foundation for Research and Technology - Hellas (“ICS”)
Abstract: According to an embodiment of the invention, a system for identifying when a running speed of an integrated circuit is within an applied clock speed is provided. A monotonic circuit is configured to receive input data and transmit output data. A completion detection circuit is configured to generate a completion detection signal for the monotonic circuit. A comparator is configured to compare at least the completion detection signal and a clock signal, and configured to emit an error signal if the clock signal arrives before the completion detection signal. A synchronous circuit element is configured to receive at least a portion of the output data and configured to be clock driven by the clock signal. The error signal represents that the clock speed is faster than an operating speed of the monotonic circuit.
Type:
Application
Filed:
January 12, 2006
Publication date:
September 28, 2006
Applicant:
Institute of Computer Science, Foundation for Research and Technology - Hellas ("ICS")
Abstract: According to one embodiment of the present invention, a system for identifying a running speed of an integrated circuit is provided. An asynchronous multi-rail circuit is configured to receive input data and transmit output data. A completion detection circuit is configured to generate a completion detection signal for the asynchronous multi-rail circuit. A variable clock generator configured to be driven by at least the completion detection signal. A synchronous circuit element configured to receive at least a portion of the output data and configured to be clock driven by a clock signal from the variable clock generator. A period of the clock signal represents a running speed of the asynchronous circuit.
Type:
Application
Filed:
December 23, 2005
Publication date:
July 13, 2006
Applicant:
Institute of Computer Science, Foundation for Research and Technology - Hellas ("ICS")