Abstract: A processor-implemented method for sound characterization is described. In one implementation, time-frequency transform of each of a plurality of sound signals from one or more sources, the sound signals being detected by a plurality of sensing devices, is derived. One or more single-source constant-time analysis zones based at least on correlation between the time-frequency transform signals from a pair of sensing devices are detected. At least one direction of arrival for each source in the detected single source analysis zones are detected. A histogram of the estimated directions of arrival is created and an estimate of a number of the sound sources and corresponding directions of arrival are generated based at least on the histogram.

Abstract: A processor-implemented method for spatial sound localization and isolation is described. The method includes segmenting, via a processor, each of a plurality of source signals detected by a plurality of sensors, into a plurality of time frames. For each time frame, the method further includes obtaining, via a processor, a plurality of direction of arrival (DOA) estimates from the plurality of sensors, discretizing an area of interest into a plurality of grid points, calculating, via the processor, DOA at each of grid points, comparing, via the processor, the DOA estimates with the computed DOAs. If the number of sources is more than 1, the method includes obtaining via the processor, a plurality of combinations of DOA estimates, from amongst the plurality of combinations, estimating, via the processor, one or more initial candidate locations corresponding to each of the combinations, selecting location of the sources from amongst the initial candidate locations.

Abstract: A method for storage input/output (I/O) path configuration in a system that includes at least one storage device in network communication with at least one computer processor; the method comprising providing in the I/O path into at least: (a) a block-based kernel-level filesystem, (b) an I/O cache module controlling an I/O cache implemented on a first computer readable medium, (c) a journaling module, and (d) a storage cache module controlling a storage cache implemented on a second computer readable medium, the second computer readable medium having a lower read/write speed than the first computer readable medium. Furthermore, the steps of translating by the filesystem, based on computer executable instructions executed by the at least one processor, a file I/O request made by an application executed by the at least one computer processor into a block I/O request and fulfilling by the at least one processor the block I/O request from one of the I/O cache and the storage cache complete the I/O operation.

Abstract: This disclosure details the implementation of apparatuses, methods and systems for audio processing and transmission. Some implementations of the system are configured to provide a method for encoding an arbitrary number of audio source signals using only a small amount of (transmitted or stored) information, while facilitating high-quality audio playback at the decoder side. Some implementations may be configured to implement, a parametric model for retaining the essential information of each source signal (side information). After the side information is extracted, the remaining information for all source signals may be summed to create a reference signal from which noise information for the original source signals may be reconstructed. The reference signal and the side information form the new collection of information to be transmitted or stored for subsequent decoding.

Abstract: A method for storage input/output (I/O) path configuration in a system that includes at least one storage device in network communication with at least one computer processor; the method comprising providing in the I/O path into at least: (a) a block-based kernel-level filesystem, (b) an I/O cache module controlling an I/O cache implemented on a first computer readable medium, (c) a journaling module, and (d) a storage cache module controlling a storage cache implemented on a second computer readable medium, the second computer readable medium having a lower read/write speed than the first computer readable medium. Furthermore, the steps of translating by the filesystem, based on computer executable instructions executed by the at least one processor, a file I/O request made by an application executed by the at least one computer processor into a block I/O request and fulfilling by the at least one processor the block I/O request from one of the I/O cache and the storage cache complete the I/O operation.

Abstract: A computer readable storage medium includes executable instructions to receive a specification of a combinational logic circuit. The specification of the combinational logic circuit is converted to a Single-Rail un-encoded circuit and a Dual-Rail encoded circuit, which periodically encodes a null value, a first valid state and a second valid state on two wires. A logic operation of the Single-Rail un-encoded circuit transpires during processing of a null value by the Dual-Rail encoded circuit.

Abstract: A computer readable storage medium includes executable instructions to construct a delay element to replicate the timing of critical gates and paths within a segment of an asynchronous circuit. The rise and fall delay mismatch of the delay element is minimized without obeying timing constraints. The position of each output of the delay element is determined to include a globally shared node within the segment and a non-shared local node in the segment.

Abstract: A method for managing data and corresponding computer program are provided.

Abstract: A computer readable storage medium includes executable instructions to analyze an asynchronous, multi-rail digital circuit to identify a gating sub-circuit and a gated sub-circuit. The asynchronous, multi-rail digital circuit is transformed to segregate the gating sub-circuit and the gated sub-circuit.

Abstract: A method of converting a Boolean logic circuit into an asynchronous multi-rail circuit is provided. A Boolean logic circuit is converted into a first multi-rail circuit using at least Shannon's expansion. The first multi-rail circuit is technology mapped into a second multi-rail circuit. Completion detection circuitry is added which receives the primary outputs of the second multi-rail circuit.

Abstract: A computer readable storage medium includes executable instructions to construct a delay element to replicate the timing of critical gates and paths within a segment of an asynchronous circuit. The rise and fall delay mismatch of the delay element is minimized without obeying timing constraints. The position of each output of the delay element is determined to include a globally shared node within the segment and a non-shared local node in the segment.

Abstract: According to an embodiment of the invention, a system for identifying when a running speed of an integrated circuit is within an applied clock speed is provided. A monotonic circuit is configured to receive input data and transmit output data. A completion detection circuit is configured to generate a completion detection signal for the monotonic circuit. A comparator is configured to compare at least the completion detection signal and a clock signal, and configured to emit an error signal if the clock signal arrives before the completion detection signal. A synchronous circuit element is configured to receive at least a portion of the output data and configured to be clock driven by the clock signal. The error signal represents that the clock speed is faster than an operating speed of the monotonic circuit.

Abstract: According to one embodiment of the present invention, a system for identifying a running speed of an integrated circuit is provided. An asynchronous multi-rail circuit is configured to receive input data and transmit output data. A completion detection circuit is configured to generate a completion detection signal for the asynchronous multi-rail circuit. A variable clock generator configured to be driven by at least the completion detection signal. A synchronous circuit element configured to receive at least a portion of the output data and configured to be clock driven by a clock signal from the variable clock generator. A period of the clock signal represents a running speed of the asynchronous circuit.