Abstract: The disclosure provides a spintronic device, a SOT-MRAM storage cell, a storage array and a in-memory computing circuit. The spintronic device includes a ferroelectric/ferromagnetic heterostructure, a magnetic tunnel junction, and a heavy metal layer between the ferroelectric/ferromagnetic heterostructure and the magnetic tunnel junction; the ferroelectric/ferromagnetic heterostructure includes a multiferroic material layer and a ferromagnetic layer arranged in a stacked manner, and the magnetic tunnel junction includes a free layer, an insulating layer and a reference layer arranged in a stacked manner, and the heavy metal layer is disposed between the ferromagnetic layer and the free layer. According to one or more embodiments of the disclosure, the spintronic device, the SOT-MRAM storage cell, the storage array and the in-memory computing circuit can realize deterministic magnetization inversion under the condition of no applied field assistance.

Abstract: An embodiment of the present disclosure provides an etching method, having the following steps: forming a modified layer having a thickness of one or several atom layers on a selected region of a surface of a semiconductor material layer by using a modifier; and removing the modified layer. When a semiconductor is processed, this method achieves precise control over the etching thickness and improves the etching rate at the same time.

Abstract: A pixel compensation circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, and an organic light-emitting diode, each of the first transistor to the sixth transistor including a drain, a source and a gate.

Abstract: A semiconductor device with a C-shaped active area and an electronic apparatus including the same is disclosed. The semiconductor device may include a first device and a second device opposite to each other on a substrate, each of which includes: a channel portion extending vertically on the substrate; source/drain portions located at the upper and lower ends of the channel portion and along the channel portion, the source/drain portions and the channel portion constitute a C-shaped structure; and a gate stack overlapping the channel portion on an inner sidewall of C-shaped structure, the gate stack has a portion surrounded by the C-shaped structure. The openings of the C-shaped structures of the two devices are opposite to each other. At least a portion of the gate stack of the first device close to the channel portion and that of the second device close to the channel portion are substantially coplanar.

Abstract: A storage unit, a method of manufacturing the storage unit, and a three-dimensional memory. The storage unit includes: a first conductivity-type substrate; a channel layer stacked on the first conductivity-type substrate in a first direction; a second conductivity-type conduction layer including a first part and a second part that are connected, the first part being located between the first conductivity-type substrate and the channel layer, and the second part being formed in a via hole passing through the channel layer; a channel passage layer penetrating the channel layer and the first part in a negative direction of the first direction, and extending into an interior of the first conductivity-type substrate; and an insulating layer located in the channel layer and surrounding a periphery of the channel passage layer. The first conductivity-type substrate and the second conductivity-type conduction layer provide carriers required for reading and erasing operations, respectively.

Abstract: Disclosed are an artificial sensory nervous circuit and a manufacturing method thereof. The artificial sensory nervous circuit includes a sensor (S), a first memristor (RS), and a neuron circuit, where the first memristor (RS) has a unidirectional resistance characteristic. The sensor (S) is configured to sensing an external signal and generating an excitation signal according to the external signal. The first memristor (RS) is configured to generating a response signal according to the excitation signal. The neuron circuit is configured to perform charging and discharging according to the response signal so as to output a pulse signal. With the artificial sensory nervous circuit and the manufacturing method thereof, sensitivity and habituation characteristics of biological perception are realized by using a simple circuit.

Abstract: Disclosed is an afferent neuron circuit, which includes: a resistance Rc and a volatile threshold switching device TS, wherein the volatile threshold switching device TS is provided with a parasitic capacitor Cparasitic; a first end of the resistance Rc serves as a signal input terminal, and a second end of the resistance Rc serves as a signal output terminal; and a first end of the volatile threshold switching device TS is connected to the signal output terminal, and a second end of the volatile threshold switching device TS is grounded. The afferent neuron circuit provided in the content of the present disclosure has a simple structure and good scalability and is suitable for large-scale integration.

Abstract: The present disclosure discloses a storage method, a data processing method, a device and an apparatus based on a non-volatile memory, the method comprising: acquiring a weight value that needs to be stored in the non-volatile memory; determining a conductivity value corresponding to the weight value according to a first conversion method if the non-volatile memory is a high-resistance storage device; determining a conductivity value corresponding to the weight value according to a second conversion method which is different from the first conversion method if the non-volatile memory is a low-resistance memory device; and setting the non-volatile memory according to the conductivity value to store the weight value.

Abstract: A semiconductor device, including: a substrate; a first source/drain layer, a channel layer, and a second source/drain layer sequentially stacked on the substrate and adjacent to each other, and a gate stack formed around an outer circumference of the channel layer; wherein at least one interface structure is formed in at least one of the first source/drain layer and the second source/drain layer, the conduction band energy levels at both sides of the interface structure are different and/or the valence band energy levels are different.

Abstract: A semiconductor memory device, a method of manufacturing the same, and an electronic device including the semiconductor memory device are disclosed.

Abstract: A Static Random Access Memory (SRAM) cell that may include a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first pass-gate transistor and a second pass-gate transistor provided at two levels on a substrate. The respective transistors may be vertical transistors. The first pull-up transistor and the second pull-up transistor may be provided at a first level, and the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor and the second pass-gate transistor may be provided at a second level different from the first level. A region where the first pull-up transistor and the second pull-up transistor are located and a region where the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor and the second pass-gate transistor are located may at least partially overlap in a vertical direction with respect to an upper surface of the substrate.

Abstract: An interconnection structure and a method of manufacturing the same, and an electronic device including the interconnection structure are provided.

Abstract: The present disclosure provides a method and an apparatus for obtaining surface potential.

Abstract: A semiconductor memory device including a substrate; an array of memory cells arranged in rows and columns on the substrate, each memory cell comprising a vertical pillar-shaped active region having upper and lower source/drain regions and a channel region, and a gate stack formed around the channel region; a plurality of bit lines on the substrate, each bit line located below a column of memory cells and electrically connected to the lower source/drain regions of the memory cells; and a plurality of word lines on the substrate, each word line extending in a row direction and connected to gate conductors of the memory cells in a row of memory cells, each word line comprising first portions extending along peripheries of the memory cells and second portions extending between the first portions, the first portions of the word line extending in a conformal manner with sidewalls of the upper source/drain regions.

Abstract: There are provided a vertical semiconductor device, a method of manufacturing the same, and an electronic device including the same.

Abstract: There are provided a nanometer semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. According to an embodiment, the semiconductor device may include: a substrate; at least one nanowire spaced apart from the substrate; at least one semiconductor layer, each formed around a periphery of respective one of the at least one nanowire to at least partially surround the corresponding nanowire, wherein the semiconductor layer(s) formed around the respective nanowire(s) are separated from each other; an isolation layer formed on the substrate, exposing the at least one semiconductor layer; and a gate stack formed on the isolation layer and intersecting the at least one semiconductor layer, wherein the gate stack includes a gate dielectric layer at least partially surrounding a periphery of respective one of the at least one semiconductor layer and a gate conductor layer.

Abstract: A memory device may include first and second pillar-shaped active regions formed on a substrate and extending upward. The first and second active regions are arranged in a first array and a second array, respectively. Each of the first active regions comprises alternatively stacked source/drain layers and channel layers, wherein the channel layers of the respective first active regions at a corresponding level are substantially coplanar with each other, and the source/drain layers of the respective first active regions at a corresponding level are substantially coplanar with each other. Each of the second active regions comprises an active semiconductor layer extending integrally. The memory device may include multiple layers of first storage gate stacks surrounding peripheries of and being substantially coplanar with the respective levels of the channel layers, and multiple layers of second storage gate stacks which surround peripheries of the respective second active regions.

Abstract: A GaN-based superjunction vertical power transistor and a manufacturing method thereof. The transistor includes: a N?-GaN layer; a first P-GaN layer as a current blocking layer, formed on the N?-GaN layer and having a gate region window; and a thin barrier Al(In, Ga)N/GaN heterostructure conformally formed on the current blocking layer and filling the bottom and one or more sidewalls of the gate region window, wherein the N?-GaN layer has an etched groove completely or partially filled with a second P-type GaN layer, an N+-GaN layer is formed under the second P-type GaN layer, and the N+-GaN layer is in direct contact with the second P-type GaN layer and the N?-GaN layer to form a superjunction composite structure.

Abstract: A method of manufacturing a semiconductor device may include: forming a fin-shaped structure on a substrate; forming a supporting layer on the substrate having the fin-shaped structure formed thereon, and patterning the supporting layer into a supporting portion extending from a surface of the substrate to a surface of the fin-shaped structure and thus physically connecting them; removing a portion of the fin-shaped structure close to the substrate to form a first semiconductor layer spaced apart from the substrate; growing a second semiconductor layer with the first semiconductor layer as a seed layer; and in at least a fraction of the longitudinal extent, removing the first semiconductor layer, and cutting off the second semiconductor layer on sides of the first semiconductor layer away from the substrate and close to the substrate, respectively, so that the cut-off second semiconductor layer acts as a fin of the device.

Abstract: A semiconductor arrangement includes: a substrate; fins formed on the substrate and extending in a first direction; gate stacks formed on the substrate and each extending in a second direction crossing the first direction to intersect at least one of the fins, and dummy gates composed of a dielectric and extending in the second direction; spacers formed on sidewalls of the gate stacks and the dummy gates; and dielectric disposed between first and second ones of the gate stacks in the second direction to electrically isolate the first and second gate stacks. The dielectric is disposed in a space surrounded by respective spacers of the first and second gate stacks which extend integrally. At least a portion of an interval between the first and second gate stacks in the second direction is less than a line interval achievable by lithography in a process of manufacturing the semiconductor arrangement.