Abstract: A semiconductor device and a method for manufacturing the same. A first electrode layer, a semiconductor layer, and a second electrode layer are formed on a substrate. The semiconductor layer is etched form a sidewall to form a cavity. A channel layer is formed at the cavity and sidewalls of the first electrode layer and the second electrode layer. The channel layer includes a first channel part located in the cavity and a second channel part located outside the cavity. The first channel part is filled with a dummy gate layer. The dummy gate layer is etched from a sidewall. The second channel part and the first channel part, which is in contact with upper and lower surfaces of the dummy gate layer are removed to form a recess. The recess is filled with a dielectric material to form an isolation sidewall.

Abstract: Provided are a nanowire/nanosheet device with a support portion, a method of manufacturing the same, and an electronic apparatus including the nanowire/nanosheet device.

Abstract: Provided are a NOR-type memory device, a manufacturing method, and an electronic device. The device includes: a plurality of gate stacks extending vertically on a substrate, wherein the gate stack includes a first gate conductor layer and a first filling layer; at least one device layer surrounding a periphery of the gate stack and extending along a sidewall of the gate stack; and a single-crystal vertical channel on a side of the device layer close to the gate stack and in contact with the first filling layer. At least one side surface of the gate stack in the vertical direction is a (100) or (110) crystal plane; and/or the body region includes a second filling layer or the body region includes a second gate conductor layer and a third filling layer, wherein at least one of first and third filling layers is a storage functional layer.

Abstract: A reconfigurable PUF device based on fully electric field-controlled domain wall motion includes a voltage control layer, upper electrodes, a lower electrode, antiferromagnetic pinning layers, and a magnetic tunnel junction (MTJ). The MTJ includes, from bottom to top, a ferromagnetic reference layer, a potential barrier tunneling layer and a ferromagnetic free layer. In the device, an energy potential well is formed in a middle portion of the ferromagnetic free layer by applying a voltage to the voltage control layer to control magnetic anisotropy, and a current is fed into either of the upper electrodes to drive generation of the magnetic domain walls and pin the magnetic domain walls to the potential well. After the voltage is removed, the potential well is lowered so that the magnetic domain walls are in a metastable state, thereby either a high resistance state or a low resistance state is randomly obtained.

Abstract: A magnetoresistive memory cell includes a first magnetic tunnel junction, a second magnetic tunnel junction and a metal layer. The first magnetic tunnel junction and the second magnetic tunnel junction each are disposed on the metal layer; the metal layer is configured to pass write current, a projection line of an easy axis of the first magnetic tunnel junction on a plane where the metal layer is located forms a first angle against a direction of the write current, and a projection line of an easy axis of the second magnetic tunnel junction on the plane where the metal layer is located forms a second angle against a direction opposite to the direction of the write current; the first angle and the second angle are all less than 90°; the first magnetic tunnel junction and the second magnetic tunnel junction are configured to pass read current.

Abstract: The folded channel gallium nitride based field-effect transistor includes: a base layer; a multi-heterojunction layer, including a channel layer and a barrier layer alternatingly stacked from bottom to top on a gallium nitride semi-insulating layer; a gallium nitride control layer on the multi-heterojunction layer and extending from one side of the channel region to at least a part of the groove; a current collapse suppression structure formed on the multi-heterojunction layer on another side of the channel region; a source electrode and a drain electrode that are respectively in contact with two sides of the multi-heterojunction layer on the gallium nitride semi-insulating layer; a gate electrode formed on the multi-heterojunction layer between the source electrode and the gallium nitride control layer; and a connecting structure passing over the gate electrode to electrically connect to the source electrode and the gallium nitride control layer.

Abstract: Disclosed is a neural network operation device, including: an operation array including operation units, wherein each operation unit includes: a source terminal, a drain terminal, a gate electrode, a threshold voltage adjustment layer under the gate electrode, and a channel region extending between a source region and a drain region, the threshold voltage adjustment layer is located on the channel region. The gate electrodes of each column of operation units of the operation array are connected together, and each column is used to adjust a weight value according to a threshold voltage adjusted by the threshold voltage adjustment layer. The threshold voltage adjustment layer is a ferroelectric layer.

Abstract: A storage unit, a method of manufacturing the storage unit, and a three-dimensional memory. The storage unit includes: a first conductivity-type substrate; a channel layer stacked on the first conductivity-type substrate in a first direction; a second conductivity-type conduction layer including a first part and a second part that are connected, the first part being located between the first conductivity-type substrate and the channel layer, and the second part being formed in a via hole passing through the channel layer; a channel passage layer penetrating the channel layer and the first part in a negative direction of the first direction, and extending into an interior of the first conductivity-type substrate; and an insulating layer located in the channel layer and surrounding a periphery of the channel passage layer. The first conductivity-type substrate and the second conductivity-type conduction layer provide carriers required for reading and erasing operations, respectively.

Abstract: The present disclosure discloses a power device including at least one vacuum packaged unit structure. The unit structure comprises a silicon substrate (100) and an emitter (200), a light modulator (300) and a collector (400) formed on the silicon substrate (100). On the one hand, the unified silicon-based process is compatible with the existing commercial process, so that it is easy for integration, simple for manufacture, and low in cost; on the other hand, the light modulator (300) is introduced and formed on the silicon substrate by a silicon-based process, which enhances field emission efficiency of the emitter (200), offsets the inconsistency of distances between the tips of the emitters (200) and the collector (400) caused by unevenness of the emitters, and increases the process redundancy of the cold cathode emitter.

Abstract: Provided is an L-shaped stepped word line structure including: L-shaped word line units, each including a long side extending in a second direction and arranged adjacent to a gate line slit, and a short side extending in a first direction. A word line terminal included in the short side is formed in a stepped stacked layer structure including stacked layer pairs formed of an insulating material, a region close to the gate line slit in a stacked layer of each stacked layer pair serves as a replacement metal region including a short side region surface/internal metal layer respectively located on a surface/in an interior. In a first direction, a length of the short side region surface metal layer is greater than that of the short side region internal metal layer, and the word line terminal corresponds to the short side region surface metal layer.

Abstract: An encryption method includes: receiving cipher data which is binary data; determining target components in a resistive memory array according to values of respective bits in the cipher data; determining current values generated by respective columns of components according to the target components; and generating key data according to the current values generated by the respective columns of components. The present disclosure can effectively reduce computing power and power consumption of an encryption process in an edge device.

Abstract: The vertical MOSFET device includes: an active region including a first source/drain layer, a channel layer and a second source/drain layer vertically stacked on a substrate in sequence, wherein an outer periphery of the channel layer is recessed with respect to outer peripheries of the first source/drain layer and the second source/drain layer; a spacing layer including an upper spacing layer and a lower spacing layer, wherein the upper spacing layer and the lower spacing layer are both in contact with a side surface of the channel layer and are not in communication with each other; and a gate stack formed at least on a lateral outer periphery of the channel layer and embedded in a groove space between the upper spacing layer and the lower spacing layer.

Abstract: Disclosed are a semiconductor device, a method for manufacturing the same, an integrated circuit, and an electronic apparatus. The semiconductor device includes: a substrate; an active region on the substrate, the active region includes a first source and drain layer, a channel layer, and a second source and drain layer sequentially stacked on the substrate; a gate stack formed around an outer periphery of the channel layer; and an intermediate dielectric layer and a second conductive layer around an outer periphery of the gate stack and an outer periphery of the active region. The device and method provided by the present disclosure are used to solve the technical problem that the performances of the vertical device in the related art need to be improved. A semiconductor device with better performances is provided.

Abstract: An encryption method includes: receiving cipher data which is binary data; determining target components in a resistive memory array according to values of respective bits in the cipher data; determining current values generated by respective columns of components according to the target components; and generating key data according to the current values generated by the respective columns of components. The present disclosure can effectively reduce computing power and power consumption of an encryption process in an edge device.

Abstract: A read-write method includes: sequentially writing, in a first direction, a code word obtained by information-bit encoding into a target memory cell in each layer of memory cell array in the three-dimensional memory; randomly reading the target memory cell in each layer of memory cell array, or sequentially reading the target memory cell in each layer of memory cell array in a second direction; and determining an LLR value of a current target memory cell according to a storage time corresponding to the current target memory cell when reading, a threshold voltage partition corresponding to the current target memory cell when reading, a comprehensive distribution state corresponding to the current target memory cell when reading, and a pre-established LLR table, so as to perform a soft decoding operation on the code word in the current target memory cell based on the LLR value of the current target memory cell.

Abstract: A compact vertical semiconductor device and a manufacturing method thereof, and an electronic apparatus including the semiconductor device are provided. According to the embodiments, the vertical semiconductor device may include: a plurality of vertical unit devices stacked on each other, in which the unit devices include respective gate stacks extending in a lateral direction, and each of the gate stacks includes a main body, an end portion, and a connection portion located between the main body and the end portion, and in a top view, a periphery of the connection portion is recessed relative to peripheries of the main body and the end portion; and a contact portion located on the end portion of each of the gate stacks, in which the contact portion is in contact with the end portion.

Abstract: The method includes: reading a memory cell having a encoded information bit, so as to obtain an LLR value of a current memory cell with reference to a pre-established LLR table according to a storage time, a threshold voltage partition and a comprehensive distribution corresponding to the current memory cell during reading; and performing a soft decoding operation on a codeword in the memory cell having the encoded information bit according to the read LLR value of the current memory cell, wherein the comprehensive distribution of the current memory cell is determined according to an influence of a memory cell adjacent to the current memory cell on a distribution of the current memory cell; an input of the pre-established LLR table comprises a storage time, a threshold voltage partition and a comprehensive distribution, and an output of the pre-established LLR table comprises an LLR value.

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof, and an electronic device including the semiconductor device. The semiconductor device may include: a substrate; a first source/drain region, a channel region and a second source/drain region stacked sequentially on the substrate and adjacent to each other, and a gate stack formed around an outer periphery of the channel region; wherein the gate stack has a thickness varying in a direction perpendicular to a top surface of the substrate.

Abstract: An interconnection structure and a method of manufacturing the same, and an electronic device including the interconnection structure are provided.

Abstract: A data readout circuit of a RRAM includes: an adaptive current sense amplifier (CSA) and a reference current generator, the adaptive CSA is configured to electrically connect to the RRAM, and the adaptive CSA is electrically connected to the reference current generator; the reference current generator is configured to generate a basic reference current; the adaptive CSA is configured to obtain a reference current according to the basic reference current and a bit-line current of the RRAM; and the adaptive CSA is configured to compare the size of the reference current and that of the bit-line current so as to read out stored data. The present disclosure can improve the problem of data readout error due to the degradation of high resistance state of the RRAM.