Patents Assigned to Institute of Microelectronics, National University of Singapore
  • Patent number: 5930595
    Abstract: A novel process for fabricating an integrated circuit sensor/actuator is described. Silicon islands are created by forming deep trenches in a substrate and lining the trenches with oxide. This forms silicon islands substantially surrounded by electrically isolating oxide. The anchor portion of the sensor/actuator beams is connected to the islands and is released from the substrate and therefore is also electrically isolated from the substrate. The IC sensor/actuator is manufactured by forming deep trenches in a substrate.
    Type: Grant
    Filed: October 15, 1997
    Date of Patent: July 27, 1999
    Assignee: Institute of Microelectronics National University of Singapore
    Inventors: Uppili Sridhar, Liu Lian Jun, Foo Pang Dow, Lo Yong Hong, Maio Yu Bo
  • Patent number: 5854573
    Abstract: A low-voltage multipath-miller-zero-compensated operational amplifier is disclosed which includes a class AB front stage and a class AB back stage. The front stage has an inverted input, a non-inverted input, an inverted output, and a non-inverted output. The back stage has an output and input, which input is connected to the non-inverted output of the front stage. The output of the back stage is connected to the inverted output of the front stage. A capacitor is coupled in a feedback loop between the output and inverted input of the back stage. An operational amplifier in accordance with the present invention is particularly well-suited for use in switched-capacitor filters, continuous-time filters, microwave medical applications and general purpose amplification applications.
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: December 29, 1998
    Assignee: Institute of Microelectronics National University of Singapore
    Inventor: Pak Kwong Chan
  • Patent number: 5773878
    Abstract: The present invention relates to a lead frame design for IC packaging to reduce chip stress and deformation and to improve mold filling. The die-pad is split into several sections which are jointed together by flexible expansion joints. The split die-pad allows relative motion between the pad and the chip during die attach cure. It also breaks down the total die pad area (and length) that is rigidly attached to the chip into smaller sections. These two factors reduce the magnitude of coefficient-of-thermal expansion (CTE) mismatch and out of plane deformation of the assembly, resulting in lower chip stress and deformation and improved package moldability.
    Type: Grant
    Filed: January 4, 1996
    Date of Patent: June 30, 1998
    Assignee: Institute of Microelectronics National University of Singapore
    Inventors: Thiam Beng Lim, Sarvotham M. Bhandarkar
  • Patent number: 5649077
    Abstract: The present invention describes a circuit for performing high speed forward Scaled Discrete Cosine Transform (SDCT) and inverse Scaled Discrete Cosine Transform (ISDCT) in pipeline architecture which is ideally, but not exclusively, used for compressing and decompressing large volume image data in real time. A high throughput of image data transform and inverse transform is achieved with a relatively slow internal clock. The four stage pipeline architecture of the present invention requires no more than five multipliers in rendering either the forward SDCT or inverse SDCT coefficients. The lower-order SDCT's for either the forward or the inverse direction are imbedded in the higher-order forward SDCT or inverse SDCT respectively. By taking advantage of the recursive properties of the SDCT's, a larger size SDCT can be always implemented by using a combination of variants of smaller size SDCT.
    Type: Grant
    Filed: April 15, 1996
    Date of Patent: July 15, 1997
    Assignee: Institute of Microelectronics, National University of Singapore
    Inventors: Bill Ngoc On, Mandayam A. Narasimhan
  • Patent number: 5475336
    Abstract: A small and easy to fabricate programmable current source correction circuit. The correction circuit consists of a first current division circuit for establishing a reference current; a programmable correction current circuit for establishing the amount of correction current required; a second current division circuit for further reducing the reference current into smaller step or resolution; and a source-sink controlling circuit for determining whether the present invention is to operate as a current sink or current source. The present invention consists of substantially less number of circuit modules and can be fully integrated into a single chip which requires substantially smaller chip area and can operates at a substantially higher frequency compared to prior art.
    Type: Grant
    Filed: December 19, 1994
    Date of Patent: December 12, 1995
    Assignee: Institute of Microelectronics, National University of Singapore
    Inventors: Raminder J. Singh, Ansuya P. Bhatt, Khen S. Tan