Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

Abstract: A power line communication (PLC) device comprises a processor and a memory coupled to the processor. The memory is configured to store program instructions executable by the processor to cause the PLC device perform operations. One or more time slots are sequentially scan in each of a plurality of frequency bands. A packet transmitted by a second PLC device to the PLC device over one of the plurality of frequency bands is detected. Additional packets received from the second PLC device across the plurality of frequency bands based, at least in part, upon the detected packet are synchronized. The additional packets are organized in a plurality of frames, each of the plurality of frames having been transmitted by the second PLC device to the PLC device over a respective one of the plurality of frequency bands.

Abstract: A method for fabricating a semiconductor proximity sensor includes providing a flat leadframe with a first and a second surface. The second surface is solderable. The leadframe includes a first and a second pad, a plurality of leads, and fingers framing the first pad. The fingers are spaced from the first pad by a gap which is filled with a clear molding compound. A light-emitting diode (LED) chip is assembled on the first pad and encapsulated by a first volume of the clear compound. The first volume outlined as a first lens. A sensor chip is assembled on the second pad and encapsulated by a second volume of the clear compound. The second volume outlined as a second lens. Opaque molding compound fills the space between the first and second volumes of clear compound, forms shutters for the first and second lenses, and forms walls rising from the frame of fingers to create an enclosed cavity for the LED.

Abstract: Within a display area of a touchscreen, multiple elements are displayed. A location is detected of a physical touch within the display area. In response to determining that an ambiguity exists about which of the elements is being targeted by the physical touch, a menu is displayed on the touchscreen for prompting a user to select between ones of the elements that are at least partially displayed within a specified area around the location. The ambiguity is resolved by receiving a selection from the user via the menu.

Abstract: A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from the TAP controller into a single signal and communicating the TDI and TMS signals of the single signal on the rising and falling edges of the TCK driving the DDR interface. The TAP domain may be coupled to the TAP controller in a point to point fashion or in an addressable bus fashion. The access to the TAP domain may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Abstract: An integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell.

Abstract: A power supply system (200) has a QFN leadframe with leads and a pad (201). The pad surface facing a circuit board has a portion recessed with a depth (270) and an outline suitable for attaching side-by-side the sync (210) and the control (220) FET semiconductor chips. The input terminal (220a) of the control FET and the grounded output terminal (210a) of the sync FET are coplanar with the un-recessed portion of the pad (switch node terminal) so that all terminals can be directly attached to contacts of a circuit board. A driver-and-control chip (230) is vertically stacked to the opposite pad surface and encapsulated in a packaging compound (290).

Abstract: The invention is a method of operating a system having multiple finite state machines and a controller. Each finite state machine enters an offline state upon detection of anomalous operation. The controller detects whether all finite state machines are offline. The controller transmits an online activation event signal to each finite state machine when all are offline. Each finite state machine evaluates entering the online state if current conditions permit. Reentering the online state includes loading a predetermined set of operating parameters. The finite state machines are responsive only to a reset event and an online activation event when in the offline state.

Abstract: Several circuits and methods implemented to perform signal quality estimation and control are disclosed. In an embodiment, a method of signal quality estimation includes generating a demodulated signal associated with a radio signal. Information associated with a quality of the demodulated signal is accessed. Further, a value of radio frequency signal-to-noise ratio (RF-SNR) for the radio signal based on the information is estimated. Estimating the value of RF-SNR facilitates in signal quality estimation of the radio signal and control of the demodulated signal.

Abstract: A device and method for controlling radio power in a wireless sensor network. A wireless sensor device includes a wireless transceiver, a white list generator, and power control logic. The wireless transceiver is configured to transmit and receive via a wireless sensor network. The white list generator configured to identify wireless sensor nodes that communicate directly with the wireless sensor device via the wireless sensor network, to identify time slots assigned for communication between the wireless sensor device and each of the identified wireless sensor nodes, and to create and maintain a list of the identified wireless sensor nodes and corresponding time slots. The power control logic is configured to power the transceiver for reception of transmissions from each identified wireless sensor node based on the identified time slots corresponding to the identified wireless sensor node provided in the list.

Abstract: A method includes pulsating a magnetic field at a first location associated with an external surface of a wall containing magnetic material. The method also includes measuring at least one characteristic of the pulsating magnetic field at a second location associated with the external surface of the wall. The at least one characteristic changes based on corrosion on an internal surface the wall between the first and second locations. The magnetic field could be pulsated by applying an AC signal to a conductive coil or by vibrating a magnet. The method could also include analyzing the at least one measured characteristic to identify an amount of the corrosion and/or a change in the amount of the corrosion. Use of the internal surface the wall could be modified based on the amount or change of the corrosion. Multiple magnetic fields can be generated at multiple first locations, and the at least one characteristic can be measured at multiple second locations.

Abstract: A multi-level, multi-branch outphasing amplifier (20-1) includes a first branch group circuit (22-1) including a first branch circuit (11) receiving a first RF input signal (S1(t)) and first control information (S11—Ctrl=VDD) and a second branch circuit (12) receiving the first input signal and second control information (S12—Ctrl). Each of the first (11) and second (12) branch circuits includes a power amplifier. The second control information enables the second branch circuit to be switched on or off while the first branch circuit (12) remains on. A second branch group circuit (22-2) includes a third branch circuit (21) receiving a second RF input signal (S2(t)) and third control information (S21—Ctrl=VDD) and a fourth branch circuit (22) receiving the second input signal (S2(t)) and fourth control information (S22—Ctrl). Each of the third and fourth branch circuits includes a power amplifier.

Abstract: An assembly for inspecting machine parts used in the production of semiconductor devices, such as integrated circuit (IC) dies. The assembly includes a laser scanning apparatus adapted to precisely measure predetermined parameters of the machine parts.

Abstract: A cell within cellular network includes user equipments (UEs) that transmit data to a base station (eNB). Over a period of time, not all of the UEs will have data to transmit. The UEs are tracked as a scheduled portion and an unscheduled portion, wherein a UE is included in the scheduled portion in response to receiving a scheduling request from the UE. Synchronization is maintained between the eNB and each UE in the scheduled portion by sending a timing adjustment (TA) command if needed. Synchronization is maintained between the eNB and each UE in the unscheduled portion by allocating a periodic reference signal (sync-RS) to each UE in the unscheduled portion and by sending a respective timing adjustment (TA) command if needed to each respective UE in the unscheduled portion in response to a respective sync-RS received from each UE in the unscheduled portion.

Abstract: A packaged semiconductor device including a leadframe made of a first metal, the leadframe including structures with surfaces and sidewalls; capacitors attached to surface portions of the leadframe structures, the capacitors having sidewalls coplanar with structure sidewalls; the capacitors including a foil of conductive material attached to the structure surface, the conductive material having pores covered by oxide and filled with conductive polymer, the capacitors topped by electrodes made of a second metal.

Abstract: A method of quantization matrix compression in a video encoder is provided that includes preprocessing a quantization matrix by performing at least one selected from down-sampling the quantization matrix and imposing 135 degree symmetry on the quantization matrix, performing zigzag scanning on the pre-processed quantization matrix to generate a one dimensional (1D) sequence, predicting the 1D sequence to generate a residual 1D sequence, and coding the residual 1D sequence using kth order exp-Golomb coding to generate a compressed quantization matrix, wherein k?0.

Abstract: A multifunction antenna is described in which the multifunction antenna is divided into a first segment and a second segment by an impedance circuit that produces low impedance at a low frequency and high impedance at a high frequency. A high frequency radio frequency (HF-RF) signal may be transmitted or received using only the first segment of the multifunction antenna from a HF-RF transceiver by blocking the HF-RF signal from the second segment by the impedance circuit. A low frequency radio frequency (LF-RF) signal may be received using both the first segment and the second segment of the multifunction antenna by passing the LF-RF signal through the impedance circuit.

Abstract: Amplifier circuits and methods of cancelling the Miller effects in amplifiers are disclosed herein. An embodiment of an amplifier circuit includes an input and an output. An amplifier is connected between the input and the output of the circuit. A voltage source is connected to the output, wherein the voltage source output is one hundred eighty degrees out of phase with the voltage output by the amplifier, and wherein the voltage source cancels gain due to the Miller effect of a Miller capacitance between the input and output.

Abstract: ESD protection apparatus disclosed herein include an ESD trigger circuit to sense the occurrence of an ESD event and an ESD discharge device to provide a low impedance path to ground through which to discharge energy associated with the ESD pulse. Some embodiments also include a VDD turn-on clamp to prevent the ESD discharge device from switching to a conductive state during a VDD power-on event. Some embodiments further include a VDD glitch clamp to prevent a switching pulse triggered by a transient disruption in the VDD supply from propagating to the ESD discharge device and causing the ESD discharge device to conduct in the absence of an ESD event.

Abstract: The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.