Abstract: In one embodiment, a semiconductor structure used in manufacturing a semiconductor device includes a substrate layer. The structure also includes first and second isolation regions formed by etching an oxide layer provided on the substrate layer to define an epitaxial growth surface of the substrate layer for epitaxial growth of a substrate material on the epitaxial growth surface between the first and second isolation regions. The structure also includes an active region that includes the epitaxially-grown substrate material between the first and second isolation regions, the active region formed by epitaxially growing the substrate material on the epitaxial growth surface of the substrate layer.

Abstract: Prefilters for a receiver with multiple input branches are trained in the frequency domain. The frequency response B of a conditioned channel is determined without reference to the prefilters, and the frequency response W of the prefilters is computed from the frequency response B of the conditioned channel. The prefilters suppress interference.

Abstract: A method of protecting an interconnect is provided. The method includes forming an integrated circuit structure having an interconnect, and depositing vaporized benzotriazole on the interconnect.

Abstract: A patterned plasma treatment may be provided on the chip and/or the substrate to enhance the distribution of underfill material between the chip and the substrate. The underfill material is typically dispensed after the chip is electrically connected to the substrate. The chip may be electrically connected to the substrate by an array of solder bumps, as one example. The underfill material is draw into a gap between the chip and the substrate by a capillary action. The patterned plasma-treated area formed on the chip and/or on the substrate may cause greater capillary force on the underfill material, as compared to non-plasma-treated areas. Such patterned plasma-treatment area may be designed and laid out to provide for more or better control of the underfill distribution between the chip and substrate while forming a chip package.

Abstract: An integrated circuit chip which has a plurality of pads and non-reflowable contact members to be connected by reflow attachment to external parts. Each of these contact members has a height-to-diameter ratio and uniform diameter favorable for absorbing strain under thermo-mechanical stress. The members have a solderable surface on each end and a layer of reflowable material on each end. Each member is solder-attached at one end to a chip contact pad, while the other end of each member is operable for reflow attachment to external parts.

Abstract: Various embodiments of the present invention provide systems and methods for glitch reduced circuits. As one example, a glitch reduced, variable width driver circuit is disclosed. Such circuits include a data output, and at least two transistors that each includes a gate, a first leg and a second leg. The gate of the first transistor is electrically coupled to a first combined control signal, and the gate of the second transistor is electrically coupled to a second combined control signal. The first leg of the first transistor and the first leg of the second transistor are electrically coupled to a power source, and the second leg of the first transistor and the second leg of the second transistor are electrically coupled to an output signal. The circuits further include a control circuit that combines a first control signal with the data output to create the first combined control signal, and combines a second control signal with the data output to create the second combined control signal.

Abstract: A semiconductor assembly (300) comprising a semiconductor device (301), which has a plurality of metallic contact pads (302) and an outline by sides (303). A metallic bump (304) made of reflowable metal is attached to each of these contact pads. An electrically insulating substrate (305) has a surface with a plurality of metallic terminal pads (306) in locations matching the locations of the device contact pads, and further a plurality of grooves (310) and humps (311) distributed between the terminal pad locations, complementing the distribution of the terminal pads. Each bump is further attached to its matching terminal pad, respectively; the device is thus interconnected with the substrate and spaced apart by a gap (320). Adherent polymeric material (330) containing inorganic fillers fills the gap substantially without voids.

Abstract: Reducing chemical contaminants is increasingly important for maintaining competitive production costs during fabrication of electronic devices. There is currently no production floor capability for mapping chemical contaminants across an electronic device substrate on a routine basis. A scanning surface chemical analyzer for mapping the distributions of a variety of chemicals on substrates is disclosed. The analyzer includes an array of sensors, each of which detects a single chemical or narrow range of chemicals, a scanning mechanism to provide a mapping capability, an electrical signal analyzer to collect and analyze signals from the array of sensors and generate reports of chemical distributions, and an optical desorption mechanism to amplify detection. A preferred embodiment includes an array of miniature quadrupole mass spectrometers in the sensor array. Scanning modes include whole substrate mapping, region sampling, and spot sampling of known defect sites.

Abstract: Provided are a system and method for reducing failures due to hinge memory. The method, in one embodiment, includes providing a torsional element having an amount of hinge memory, wherein the hinge memory is at least partially created using an average operational temperature. The method, in this embodiment, further includes subjecting the torsional element having the hinge memory to a temperature equal to or greater than the average operational temperature while the torsional element is in a parked state for an amount of time to reduce the amount of the hinge memory.

Abstract: A screen for use in image presentations comprises an array of transmissive elongated prisms. The screen is capable of delivering incident light, having an incident angle within a specific incident angle range, to the viewing area, while preventing ambient light to be directed to the viewing area.

Abstract: An electronic device includes a first circuit (111) operable to generate at least a first and a second channel quality indicator (CQI) vector associated with a plurality of subbands for each of at least first and second spatial codewords respectively and generate a first and a second reference CQI for the first and second spatial codewords, and operable to generate a first and a second differential subbands CQI vector for each spatial codeword and generate a differential between the second reference CQI and the first reference CQI, and further operable to form a CQI report derived from the first and the second differential subbands CQI vector for each spatial codeword as well as the differential between the second reference CQI and the first reference CQI; and a second circuit (113) operable to initiate transmission of a signal communicating the CQI report. Other electronic devices, processes and systems are also disclosed.

Abstract: Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD liner in an integrated circuit which has a higher stress than single layer PMD liners. Each layer in the inventive PMD liner is exposed to a nitrogen-containing plasma, and which has a compressive stress higher than 1300 MPa. The PMD liner of the instant invention is composed of 3 to 10 layers. The hydrogen content of the first layer may be increased to improve transistor properties such as flicker noise and Negative Bias Temperature Instabilty (NBTI). An IC containing the inventive PMD liner and a method for forming same are also claimed.

Abstract: An electronic configuration circuit includes a processing circuit (2610) operable for executing instructions and responsive to interrupt requests and operable in a plurality of execution environments (EE) selectively wherein a said execution environment (EE) is activated or suspended, a first configuration register (SCR) coupled to the processing circuit (2610) for identifying the interrupt request as an ordinary interrupt request IRQ when the execution environment (EE) is activated (EE_Active); and a second configuration register (SSM_FIQ_EE_y) for associating an identification of that execution environment (EE) with the same interrupt request, the processing circuit (2610) coupled (5910) to the second configuration register (SSM_FIQ_EE_y) to respond to the same interrupt request as a more urgent type of interrupt request when that execution environment (EE) is suspended (5920).

Abstract: Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers.

Abstract: A method of manufacturing an IC that comprises fabricating a semiconductor device. Fabricating the device includes depositing a photoresist layer on a substrate surface and implanting one or more dopant species through openings in the photoresist layer into the substrate, and, into the photoresist layer, thereby forming an implanted photoresist layer. Fabricating the device also includes removing the implanted photoresist layer. Removing the implanted photoresist layer includes exposing the implanted photoresist layer to a mixture that includes sulfuric acid, hydrogen peroxide and ozone. The mixture is at a temperature of at least about 130°.

Abstract: Shrinking dimensions of MOS transistors in integrated circuits requires tighter distributions of dopants in pocket regions from halo ion implant processes. In conventional fabrication process sequences, halo dopant distributions spread during source/drain anneals. The instant invention is a method of fabricating MOS transistors in an integrated circuit in which halo ion are performed after source/drain anneals. In the inventive method, source/drain spacers on MOS gate sidewalls are removed prior to halo ion implant processes. Spacers to offset metal silicide are formed after halo implants and may be of low-k dielectric material to reduce gate to drain capacitance. A compressive stress layer may be deposited on MOS gates after source/drain spacers are removed for greater stress transfer efficiency to the MOS gates. An integrated circuit embodying the inventive method is also disclosed.

Abstract: A spoke synchronization technique allowing for lamp-pulsing synchronizes a spoke based on sub-arrays of a spatial light modulator. The lamp pulsing occurs during the spoke synchronization; and the lamp pulse for pulsing the lamp spans substantially across the entire spoke synchronization time period.

Abstract: An image compression and decompression method compresses data based upon the data states, and decompresses the compressed data based upon the codes generated during the compression.

Abstract: A noise filter method and apparatus for producing at least one of a video or an image with reduced noise. The noise filter method includes performing noise estimation on a frame of at least one of an image or video and applying a low pass filter on the noise level according to the noise estimation, performing spatial filtration on the frame, performing motion detection on a spatially filtered frame, determining motion-to-blending factor conversion and, accordingly, performing frame blending, and outputting a frame with reduced noise.

Abstract: A system comprises storage that includes first and second data. The system also comprises circuit logic coupled to the storage. The circuit logic receives a plurality of clock signals. As a result of receiving a signal, the circuit logic uses the plurality of clock signals to obtain the first and second data and to provide the first and second data to target logic coupled to the circuit logic. The system resets the circuit logic between providing the first data and providing the second data.