Abstract: A semiconductor power device including a base plate, a ring frame disposed over the base plate, a semiconductor power die disposed on the base plate and surrounded by the ring frame, an input lead by way the semiconductor power die receives an input signal, wherein the input lead is disposed over a first portion of the ring frame, and an output lead by way an output signal generated by the semiconductor power die is sent to another device, wherein the output lead is disposed over a second portion of the ring frame. The ring frame may be comprised of a relatively high thermal conductivity material, such as beryllium-oxide (Be), silicon-carbide (SiC), diamond, aluminum nitride (AlN), or others. The ring frame produces at least one more heat path between the active region of the semiconductor power die and the base plate so as to reduce the effective thermal impedance.

Abstract: A semiconductor power device including a base plate; an input lead; an output lead; a field effect transistor (FET) power die disposed over the base plate, wherein the FET power die includes a set of source fingers, a set of drain fingers, and a set of gate fingers disposed directly over an active region, wherein the gate fingers are configured to receive an input signal from the input lead, and wherein the FET power die is configured to process the input signal to generate an output signal at the drain fingers for routing to the output lead; and electrical conductors (wirebonds or ribbons) bonded to the source and/or drain directly over the active region of the FET power die. The electrical conductors produce additional thermal paths between the active region and the base plate for thermal management of the FET power die.

Abstract: A semiconductor power device including a base plate, a semiconductor power die disposed on the base plate, an input lead by way the semiconductor power die receives an input signal, an output lead by way an output signal generated by the semiconductor power die is sent to another device, and at least one thermal substrate disposed on the base plate adjacent to the semiconductor power die, wherein a set of electrodes of the semiconductor power die are thermally and electrically coupled to a metallization layer on the thermal substrate. The thermal substrate may be comprised of a relatively high thermal conductivity material, such as beryllium-oxide (Be), silicon-carbide (SiC), diamond, aluminum nitride (AlN), or others. The thermal substrate produces at least one more heat path between the active region of the semiconductor power die and the base plate so as to reduce the effective thermal impedance.

Abstract: This disclosure relates to a packaged radio frequency (RF) power transistor that includes an internal input impedance matching circuit adapted to achieve an impedance at the input lead of the package substantially higher at the input terminal of a RF power device. In particular, the internal input impedance matching circuit includes an inductive element coupled in series with a resistive element between the input terminal of the RF power device and ground. The inductance element is adapted to counter the inherent capacitance at the input terminal of the RF power device in order to substantially increase the effective input impedance of the device. The resistive element is adapted to reduce the variation of the effective input impedance of the RF power device in order provide acceptable input impedance matching across wider frequency bandwidths.

Abstract: Disclosed is an RF power FET or HEMT including an electrically-conductive substrate, a grounding metallization layer disposed on a bottom surface of the electrically-conductive substrate, an active area comprising at least one cell including source, gate and drain electrodes disposed over a top surface of the electrically-conductive substrate, and an electrically-conductive shallow trench electrically connecting the source electrode to the grounding metallization layer by way of the electrically-conductive substrate. This configuration results in the effective RF ground being very close to the active area of the FET in order to reduce parasitic source inductance and resistance. This results in potentially higher gain, higher saturation point, higher 3rd-order intercept, more efficient combining of the input RF signal, and more efficient extraction of the output RF signal.

Abstract: A radio frequency (RF) amplifier is disclosed including an active device adapted to amplify an input signal in accordance with a gain frequency response to generate an output signal, and a dissipative circuit adapted to modify the gain frequency response by dissipating the input or output signal more so at a first frequency range than at a second frequency range. The dissipative circuit may include a resistive element, and an open circuit adapted to operate as an open at a specified frequency to substantially minimize the dissipation of the input or output signal through the resistive element at the specified frequency. The open circuit may include an open-ended transmission line having an electrical length of a half wavelength or multiple thereof at the specified frequency. Alternatively, the open circuit may include a short-ended transmission line having an electrical length of a quarter wavelength or odd multiple thereof at the specified frequency.

Abstract: A radio frequency (RF) amplifier is disclosed including an active device adapted to amplify an input signal in accordance with a gain frequency response to generate an output signal, and a dissipative circuit adapted to modify the gain frequency response by dissipating the input or output signal more so at a first frequency range than at a second frequency range. The dissipative circuit may include a resistive element, and an open circuit adapted to operate as an open at a specified frequency to substantially minimize the dissipation of the input or output signal through the resistive element at the specified frequency. The open circuit may include an open-ended transmission line having an electrical length of a half wavelength or multiple thereof at the specified frequency. Alternatively, the open circuit may include a short-ended transmission line having an electrical length of a quarter wavelength or odd multiple thereof at the specified frequency.

Abstract: An RF power amplifier is disclosed that has improved input matching or reduced return losses over a wider frequency range. The amplifier includes an input impedance matching network, a resistive element, a transistor, and an output impedance matching network. The resistive element is coupled between the input impedance matching network and the input of the transistor. The resistive element is configured to lower the quality factor (Q) of the input impedance matching network. This has the effect of reducing the input impedance variation over a given frequency range. As a result, the overall impedance matching over the given frequency range is improved, thereby reducing the input return losses. This allows the RF power amplifier to be used in wider bandwidth applications.

Abstract: An RF power amplifier is disclosed that has improved input matching or reduced return losses over a wider frequency range. The amplifier includes an input impedance matching network, a resistive element, a transistor, and an output impedance matching network. The resistive element is coupled between the input impedance matching network and the input of the transistor. The resistive element is configured to lower the quality factor (Q) of the input impedance matching network. This has the effect of reducing the input impedance variation over a given frequency range. As a result, the overall impedance matching over the given frequency range is improved, thereby reducing the input return losses. This allows the RF power amplifier to be used in wider bandwidth applications.

Abstract: Disclosed is an RF power FET or HEMT including an electrically-conductive substrate, a grounding metallization layer disposed on a bottom surface of the electrically-conductive substrate, an active area comprising at least one cell including source, gate and drain electrodes disposed over a top surface of the electrically-conductive substrate, and an electrically-conductive shallow trench electrically connecting the source electrode to the grounding metallization layer by way of the electrically-conductive substrate. This configuration results in the effective RF ground being very close to the active area of the FET in order to reduce parasitic source inductance and resistance. This results in potentially higher gain, higher saturation point, higher 3rd-order intercept, more efficient combining of the input RF signal, and more efficient extraction of the output RF signal.

Abstract: An RF/microwave circuit is configured to eliminate the physical constraint that requires a sacrifice of one output series inductor wirebond for each shunt inductor wirebond. The circuit employs a multi-level metalized substrate as part of its output impedance matching network. The lower level of the multi-level substrate serves as an intermediate connection point for the output series inductor wirebonds as it extends from the output terminal of an active device to an output metallization pad. The upper level of the multi-level substrate serves to support a DC block capacitor and as an intermediate connection point for the shunt inductor wirebonds. The multi-level substrate allows the series inductor wirebonds to be positioned at a lower height, and the shunt inductor wirebonds at a greater height. Because they are at different heights, the physical constraint of sacrificing a series wirebond per a shunt inductor wirebond can be eliminated.

Abstract: An RF/microwave circuit is configured to eliminate the physical constraint that requires a sacrifice of one output series inductor wirebond for each shunt inductor wirebond. The circuit employs a multi-level metalized substrate as part of its output impedance matching network. The lower level of the multi-level substrate serves as an intermediate connection point for the output series inductor wirebonds as it extends from the output terminal of an active device to an output metallization pad. The upper level of the multi-level substrate serves to support a DC block capacitor and as an intermediate connection point for the shunt inductor wirebonds. The multi-level substrate allows the series inductor wirebonds to be positioned at a lower height, and the shunt inductor wirebonds at a greater height. Because they are at different heights, the physical constraint of sacrificing a series wirebond per a shunt inductor wirebond can be eliminated.

Abstract: An radio frequency (RF)/microwave power amplification circuit is disclosed herein having improved power and frequency characteristics. The RF power circuit is characterized by having the output capacitance of the device resonate with a shunt inductance that is physically closer to the device than provided in conventional RF power circuits. This is realized by mounting a direct current (DC) bypass capacitor directly on the same metalized pad that the device terminal is mounted on. By doing this, the inductance associated with a wire bond connection from the device to the capacitor is eliminated or at least reduced. Also disclosed is a dual cell power circuit that consists of matching the impedance characteristics of the active cells to each other by adjusting the circuit parameters in which the active devices interact with.

Abstract: An radio frequency (RF)/microwave power amplification circuit is disclosed herein having improved power and frequency characteristics. The RF power circuit is characterized by having the output capacitance of the device resonate with a shunt inductance that is physically closer to the device than provided in conventional RF power circuits. This is realized by mounting a direct current (DC) bypass capacitor directly on the same metalized pad that the device terminal is mounted on. By doing this, the inductance associated with a wire bond connection from the device to the capacitor is eliminated or at least reduced. Also disclosed is a dual cell power circuit that consists of matching the impedance characteristics of the active cells to each other by adjusting the circuit parameters in which the active devices interact with.