Abstract: A device for detecting defective memory includes a first global word line; a second global word line; a global word-line front end, connected to the first global word line; a global word-line driver, connected to the global word-line front end and driving the first global word line; a local word-line driver, connected to the first global word line and driving a local word line; and a voltage-controlled transistor, including a first terminal connected to the first global word line, a second terminal connected to a connection line between the global word-line front end and the global word-line driver, and a third terminal outputting a test current.

Abstract: A low voltage bandgap reference circuit includes a positive temperature coefficient circuit unit, a negative temperature coefficient circuit unit and a load unit, wherein the positive temperature coefficient circuit unit comprises a first differential operational amplifier, a first, second and third transistor, a first resistor, a first and second diode, and the negative temperature coefficient circuit unit includes a second differential operational amplifier, a fourth, fifth and sixth transistor, a second resistor and a third diode. The low voltage bandgap reference circuit provides a current having a positive temperature coefficient characteristics and a current having a negative temperature coefficient characteristics to flow through the load in order to generate a stable reference voltage less affected by the temperature. Therefore, it avoids the problems of the low voltage bandgap reference circuit that can not be activated at low voltage.

Abstract: A high-speed data transmission structure includes first and second electronic units and an input/output bus. The input/output bus is electrically connected to the first and second electronic units, and includes a clock signal line and N data lines, where N is an even integer. The data lines are divided into first and second data signal line groups, each provided with the same number of data lines. In a transmit mode, the first electronic unit generates and transmits a clock signal to the clock data line, and generates output signals at each clock period of the clock signal. The output signals consist of N/2 data signals lasting for two clock periods of the clock signal, and the first and second data signal line groups alternatively receive the output signals. The second electronic unit simultaneously performs a receive mode to fetch and latch the data signals according to the clock signal.

Abstract: A low voltage bandgap reference circuit includes a positive temperature coefficient circuit unit, a negative temperature coefficient circuit unit and a load unit, wherein the positive temperature coefficient circuit unit comprises a first differential operational amplifier, a first, second and third transistor, a first resistor, a first and second diode, and the negative temperature coefficient circuit unit includes a second differential operational amplifier, a fourth, fifth and sixth transistor, a second resistor and a third diode. The low voltage bandgap reference circuit provides a current having a positive temperature coefficient characteristics and a current having a negative temperature coefficient characteristics to flow through the load unit, whereby generate a stable reference voltage thereon, which the stable reference voltage is less affected by the temperature. Therefore, it avoids the problems of the low voltage bandgap reference circuit can not be activated at low voltage.

Abstract: A package structure and method for preventing gold bonding wires from collapsing are disclosed. The structure is especially useful for those chips whose two n×1 arrays of bonding pads are on the chip center to be packaged on a BGA substrate. According to the first preferred embodiment, two dies having a redistribution layer formed thereon are introduced outer the bonding pad array on the chip so that the gold bonding wires can be divided into two sections each to connect the bonding pads with the redistribution layer and the redistribution layer with the gold fingers on the BGA substrate. According to the second embodiment, the gold bonding wires are fixed by the epoxy strips on the chips after bonding the bonding pads to the gold fingers but before pouring liquid encapsulated epoxy into a mold.

Abstract: A method of about using icons and labels on window operation platform to express status of the memory card in a card reader having multiple slots is disclosed. The AP (application software) timely sends an inquiring packet to the reader. The card reader inspects the card status and then in response to the host with a responsive packet to the host. The AP then updates the icon and label in accordance with the responsive pocket, wherein the inquiring packet and responsive packet are through SCSI Pass through mode.

Abstract: A method of making a computer booting an operation system from a flash card which is plugged in a multi-card reader having the following steps: at first, a bootable card having a master bootable record or reserve sector written a bootable pattern thereon is prepared. Then if the BIOS of the host computer requests a bootable pattern from the USB storage apparatus, the firmware of the multi-card reader is then provided a logic unit number (LUN)=0 to the host computer if there is a bootable flash card seated at a socket. The socket is not need to be the first socket but arbitrary. Thus, the USB card reader will be convenient for any user.

Abstract: A high access rate flash control provided for accessing more than one flash memory chip having different access timing specifications is disclosed. The controller comprises a read/write(R/W) pulse generator, a R/W delay chain circuit, a sampling delay chain circuit, a bi-directional feedback pad (PAD1), a data bus sampler, and a second pad (PAD 2). In an embodiment, the flash controller using a fix clock to generate synchronized Read/Write pulse which is then appropriated adjusted by the R/W delay chain circuit to provide optimum R/W control signal. The adjusted R/W signal is than outputted by a bi-directional pad to flash memory chips. With the external signal feedback function, the bi-directional pad has associated with the sampling delay chain, the time latency due to pads can be eliminated nearly. Thus, the flash controller can approach high rate to access flash chips.

Abstract: A method of making a computer booting an operation system from a flash card which is plugged in multi-card reader is disclosed. The multi-card reader does not care the card is located at first socket or not. The method comprises: at first, a bootable card having a master bootable record or reserve sector written a bootable pattern thereon is prepared. Then if the BIOS of the host computer requests a bootable pattern from the USB storage apparatus, the firmware of the multi-card reader is then provided a logic unit number (LUN)=0 to the host computer if there is a bootable flash card seated at a socket. The socket is not need to be the first socket but arbitrary. Thus, the USB card reader will be convenient for any user.

Abstract: A method of updating in system program (ISP) of an USB device is disclosed. After the USB device is connected to a host and its attribute is recognized by the host, the USB device configuration is set. The microprocessor (mp) in USB device executes the ISP codes stored in the flash memory until a first vendor command “ISP_START” is sent from the host for updating new ISP codes. The mp is then idled. Afterward, the ISP decoder handled a series of vendor commands until a vendor command “ISP_RESET” is retrieved. The series of vender commands include “ISP_INITIAL”, “ISP_ERASE_PAGE”, “ISP_INITIAL”, “ISP_PROGRAM”, “ISP_READ”, and “ISP_RESET” to program new ISP codes. The “ISP_READ” is to verify the codes programmed.