Abstract: A circuit and method for protecting an integrated circuit during positive and negative ESD events. During both positive and negative ESD events, the circuit conducts ESD current through a turned on device. The circuit includes a pad, a voltage supply rail, a field effect transistor connected across the pad and the voltage supply rail, and an enabling circuit connected across the gate of the field effect transistor and the pad. During a positive ESD event, the field effect transistor is turned on to provide a conductive path between the pad and the voltage supply rail. During a negative ESD event, the bipolar transistor inherent in the field effect transistor is turned on to provide a conductive path between the pad and the voltage supply rail.