Patents Assigned to Integrated Electronics & Packaging
  • Publication number: 20020017730
    Abstract: A thin film passive element includes at least one of a capacitance element having a plurality of conductive layers and a dielectric material layer and an inductance element formed of a patterned conductive layer is stacked on a circuit element-forming region of a semiconductor substrate provided with a plurality of connection pads and is connected to the circuit element of the circuit element-forming region.
    Type: Application
    Filed: August 8, 2001
    Publication date: February 14, 2002
    Applicant: Integrated Electronics & Packaging
    Inventors: Iwao Tahara, Ichiro Mihara, Yutaka Aoki
  • Publication number: 20010042902
    Abstract: The back surface of a semiconductor wafer having a plurality of chip-forming regions each provided with a plurality of connection pads on the surface is bonded to a dicing tape, followed by fully cutting the semiconductor wafer along a cut line so as to form a cutting groove. Then, a front side protective film is formed on the front surface. The front side protective film has an open portion exposing the central portion of the connection pad, and is filled in the cutting groove. After formation of a columnar electrode connected to the connection pad via a wiring, a sealing film is formed on the front side protective film. Further, the cutting groove filled with the front side protective film is cut in substantially the center in the width direction, followed by peeling off the dicing tape so as to form individual semiconductor devices each forming a chip.
    Type: Application
    Filed: May 15, 2001
    Publication date: November 22, 2001
    Applicant: Integrated Electronics & Packaging Technologies, Inc.
    Inventors: Takeshi Wakabayashi, Osamu Kuwabara