Abstract: A programmable gate array device (10) has a repeating block of circuitry (16) that includes a lowest metal layer. The repeating block of circuitry (16) includes a row of combinatorial blocks (20) and a row of flip flop circuitry (22). A number of metal segments (38) run perpendicular to the row of combinatorial blocks (20). The metal segments (38) are formed in a middle metal layer. A customizable metal layer forms a top metal layer (40).
Type:
Grant
Filed:
December 23, 1998
Date of Patent:
February 12, 2002
Assignee:
Integrated Logic Systems, Inc
Inventors:
Hugh Norman Chapman, Michael Robert Whaley