Abstract: Various circuits, including DC/DC converters can include an integrated soft-start circuit. The integrated soft-start circuit includes a PMOS transistor configured to receive a reference signal and control the current to a bipolar junction transistor when the reference signal is in a first state. First and second NMOS transistors are included in the soft-start circuit, and receive the reference signal to turn off (to release from reset) when the reference signal is in the first state. A capacitor coupled in parallel with one of the NMOS transistors controls the soft-start signal. Various different transistors types can be used depending on the desired implementation.

Abstract: In one embodiment of the present invention, a system includes a power stage component operable to generate an output voltage from a power source and to provide the output voltage to an electrical device. The power stage component is capable of operating in a plurality of modes depending on a level of the power source. An adaptive mode change component, coupled to the power stage, is operable to track at least one variation which affects the voltage across the electrical device and to generate at least one control signal for changing among the plurality of operating modes of the power stage component in response to the tracking.

Abstract: In one embodiment, a method is provided for preventing reverse input current from flowing into a power source.

Abstract: According to an embodiment of the present invention, a system is provided for driving at least one light-emitting diode (LED). The system includes an output terminal connectable to an anode of the LED and at which an output voltage can be provided for the LED. A driver loop, connectable to a cathode of the LED, is operable to maintain a LED current flowing through the LED at a desired level, thereby attenuating modulation error attributable to voltage variations at the cathode of the LED.

Abstract: In one aspect, a system provides gamma correction in a thin-film-transistor (TFT) liquid-crystal-display (LCD). The system includes a digital-to-analog converter operable to receive digital control data. The digital-to-analog converter is operable to provide an output voltage for gamma correction in response to the digital control data.

Abstract: According to an embodiment of the present invention, a system is provided for driving at least one light-emitting diode (LED). The system includes an output terminal connectable to an anode of the LED and at which an output voltage can be provided for the LED. A driver loop, connectable to a cathode of the LED, is operable to maintain a LED current flowing through the LED at a desired level, thereby attenuating modulation error attributable to voltage variations at the cathode of the LED.

Abstract: In one aspect, apparatus and method are provided for communicating data in the form of transmission symbols conveyed in a carrier signal, wherein each transmission symbol is from a symbol set comprising a plurality of symbols which are collectively capable of representing any combination of values for at least three bits of data, wherein each symbol of the symbol set is defined with at most one transition of signal level in the carrier signal. In another aspect, apparatus and method are provided for communicating any combination of values for at least three data bits in the form of a respective transmission symbol conveyed in a carrier signal, wherein the transmission symbol is uniquely defined by a respective combination of a signal level transition, a lack of signal level transition, a signal region, and a cross-over between signal regions in the carrier signal.

Abstract: A synchronous bus system includes a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices. The forward direction clock segment carries a forward direction clock signal, and the reverse direction clock segment carries a reverse direction clock signal. Synchronization clock circuitry, provided in each device, receives the forward direction clock signal and the reverse direction clock signal. Using the received clock signals, the synchronization clock circuitry derives a universal synchronization clock signal which is synchronous throughout all devices. Skew correction circuitry, provided in at least a portion of the devices, corrects for skew between the universal synchronization clock signal and one or more data signals for transferring data between devices.

Abstract: A controller for a writable optical media is presented. The controller includes a write control sequencer that monitors the transmission of data from a host device to the writable optical media without continuous supervision from a microcomputer. The write control sequencer monitors and controls data flow in response to descriptors which are loaded into the controller prior to the transfer by a microprocessor.

Abstract: An apparatus for providing multi-symbol signaling includes a multi-symbol encoder circuit. The multi-symbol encoder circuit is operable to encode data into a plurality of symbols, each symbol uniquely defined by a signal transition and a signal region in a carrier signal. A driver circuit, coupled to the multi-symbol encoder circuit, is operable to drive the carrier signal.

Abstract: A flash memory controller with a volatile program and data memory is disclosed. The controller loads microcode and data into the program and data memory from a flash memory array upon powerup of the controller. If an error occurs during the download or the microcode does not exist in the flash memory array, then the controller loads microcode and data into the program and data memory from the host computer. In some embodiments of the invention, an initial code is downloaded to the controller so that an evaluation of the configuration of the controller and the flash memory can be communicated to a host computer. The host computer then downloads for storage into the flash memory a tailored microcode and restarts the controller so that the tailored microcode is loaded from the flash memory and executed. In some embodiments, a protection circuit is provided to protect the microcode from accidentally being erased from the flash memory.

Abstract: A synchronous bus system includes a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices. The forward direction clock segment carries a forward direction clock signal, and the reverse direction clock segment carries a reverse direction clock signal. Synchronization clock circuitry, provided in each device, receives the forward direction clock signal and the reverse direction clock signal. Using the received clock signals, the synchronization clock circuitry derives a universal synchronization clock signal which is synchronous throughout all devices. Skew correction circuitry, provided in at least a portion of the devices, corrects for skew between the universal synchronization clock signal and one or more data signals for transferring data between devices.

Abstract: A device controller having an autodisk controller is presented. The autodisk controller in monitor mode is capable of monitoring the address of incoming data blocks and, when a target address is reached, triggers a switch of the device controller to buffer mode. In buffer mode, the autodisk controller is capable of monitoring parameters regarding incoming data blocks and reporting status or errors to a microprocessor. The autodisk controller can, for example, check for Id errors, EDC errors, copyright errors, addressing errors, or data area errors. The autodisk controller can also monitor the memory buffer and determine when it is full. The autodisk controller, therefore, relieves the microprocessor of the duties of monitoring incoming data blocks and error checking those data blocks.

Abstract: An I/O interface circuit includes an output buffer circuit and an input buffer circuit. The output buffer circuit can receive a first stream of data elements for output from the semiconductor chip, add a separate reference element for each data element in the first stream, and generate a first data transmission signal representing the data elements of the first stream and the respective reference elements. The input buffer circuit can receive a second data transmission signal representing data elements of a second stream and respective reference elements for the data elements of the second stream, sample the second data transmission signal to obtain voltage values for each data element of the second stream and the respective reference element, and interpret the voltage value for each data element of the second stream against the voltage value for the respective reference element in order to recover the data elements of the second stream.

Abstract: In accordance with this invention, a data capture circuit of a data receiver captures data from a data stream of a data transmitter operating at a different phase or frequency from the system clock of the data receiver. In one embodiment, the data receiver determines the number of clock periods of a clock signal in a data period of the data stream. Specifically, a signal detection circuit receives a signal having a periodic and distinctive feature. The period of the periodic and distinctive feature is related to the data period by a fixed scaling factor. A counter counts the number of clock periods of the clock signal between a first occurrence of the periodic and distinctive feature and a second occurrence of the periodic and distinctive feature. A multiplier/divider circuit divides or multiples the content of the first counter by the scaling factor to determine the integer clock period count. The results of the multiply or divide is stored in a count register.

Abstract: A device controller for interfacing a host computer with an external storage device has an autohost controller. The device controller, at the end of a read operation, fills a memory buffer with data blocks contiguous with the read operation. On a subsequent read operation, the autohost controller checks the subsequent read operation and, if the requested data is within the memory buffer, directs the device controller to transfer the data from the memory buffer without intervention from an external microprocessor. If the autohost controller does not intervene, the device controller operates under the control of the microprocessor, as normal.

Abstract: An advanced input/output interface is provided for an integrated circuit memory having a memory storage array accessible by signals formatted in a two-level protocol. The advanced input/output interface includes a bit compression circuit for receiving a first plurality of signals formatted in the two-level protocol and generated within the integrated circuit memory. The bit compression circuit converts the first plurality of two-level protocol signals into a first signal formatted in a multi-level protocol. A bit decompression circuit receives a second signal formatted in the multi-level protocol. The bit decompression circuit converts the second multi-level protocol signal into a second plurality of signals formatted in the two-level protocol. In one embodiment, the advanced input/output interface allows for high speed/bandwidth memory accesses while reducing the pin count and operating frequency required for operation.

Abstract: In accordance with this invention, a data capture circuit of a data receiver captures data from a data stream of a data transmitter operating at a different phase or frequency from the system clock of the data receiver. In one embodiment, the data receiver determines the number of clock periods of a clock signal in a data period of the data stream. Specifically, a signal detection circuit receives a signal having a periodic and distinctive feature. The period of the periodic and distinctive feature is related to the data period by a fixed scaling factor. A counter counts the number of clock periods of the clock signal between a first occurrence of the periodic and distinctive feature and a second occurrence of the periodic and distinctive feature. A multiplier/divider circuit divides or multiples the content of the first counter by the scaling factor to determine the integer clock period count. The results of the multiply or divide is stored in a count register.

Abstract: In accordance with this invention, an arbitration unit controls access to a shared device between a plurality devices. The arbitration unit grants access to the shared device so that both the maximum latency requirement and the minimum access requirement of the devices are satisfied. In one embodiment, a first device with high access requirements uses the precedence of a second device when the second device has a higher precedence than the first device and the second device does not request access to the shared device. Thus the first device can receive access to the shared device based on the precedence of the second device or the precedence of the first device. In another embodiment, the devices are circularly ordered to determine the precedence of each device. In accordance with circular arbitration, after the first device receives access to the shared device based on the precedence of the second device, the second device is assigned the lowest precedence.

Abstract: An embodiment of an automated cache manager includes a word/block converter, which generates a word count from a valid cache block register, a current block register, and a total block transfer register. For example, the word/block converter obtains the number of valid cache blocks and calculates a partial transfer length based on the number of valid cache blocks, the total block transfer length, and the maximum partial transfer length. The automated cache manager then initiates a partial transfer with the calculated partial transfer length.