Patents Assigned to Integrated Memory Technologies, Inc.
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Patent number: 7407857Abstract: An memory device, and method of making same, that includes source and drain regions defining a channel region therebetween. A select gate is formed over and insulated from a first portion of the channel region. A conductive floating gate is disposed over and insulated from the source region and a second portion of the channel region. A notch is formed in the floating gate bottom surface having an edge that is either aligned with an edge of the source region or is disposed over the source region. A conductive control gate is disposed adjacent to the floating gate. By having the source region terminate under the thicker insulation region provided by the notch, the breakdown voltage of the source junction is increased. Alternately, the lower portion of the floating gate is formed entirely over the source region, for producing fringing fields to control the adjacent portion of the channel region.Type: GrantFiled: January 23, 2006Date of Patent: August 5, 2008Assignee: Integrated Memory Technologies, Inc.Inventors: Ching-Shi Jeno, Ting P. Yen
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Patent number: 7199424Abstract: An memory device, and method of making same, that includes source and drain regions defining a channel region therebetween. A select gate is formed over and insulated from a first portion of the channel region. A conductive floating gate is disposed over and insulated from the source region and a second portion of the channel region. A notch is formed in the floating gate bottom surface having an edge that is either aligned with an edge of the source region or is disposed over the source region. A conductive control gate is disposed adjacent to the floating gate. By having the source region terminate under the thicker insulation region provided by the notch, the breakdown voltage of the source junction is increased. Alternately, the lower portion of the floating gate is formed entirely over the source region, for producing fringing fields to control the adjacent portion of the channel region.Type: GrantFiled: January 23, 2006Date of Patent: April 3, 2007Assignee: Integrated Memory Technologies, Inc.Inventors: Ching-Shi Jenq, Ting P. Yen
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Patent number: 7009244Abstract: An memory device, and method of making same, that includes source and drain regions defining a channel region therebetween. A select gate is formed over and insulated from a first portion of the channel region. A conductive floating gate is disposed over and insulated from the source region and a second portion of the channel region. A notch is formed in the floating gate bottom surface having an edge that is either aligned with an edge of the source region or is disposed over the source region. A conductive control gate is disposed adjacent to the floating gate. By having the source region terminate under the thicker insulation region provided by the notch, the breakdown voltage of the source junction is increased. Alternately, the lower portion of the floating gate is formed entirely over the source region, for producing fringing fields to control the adjacent portion of the channel region.Type: GrantFiled: June 28, 2004Date of Patent: March 7, 2006Assignee: Integrated Memory Technologies, Inc.Inventors: Ching-Shi Jenq, Ting P. Yen
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Patent number: 6967870Abstract: An integrated circuit memory device has an array of non-floating gate non-volatile flash cells arranged in a NOR configuration. The device further has page buffers and control circuits to operate the array in either a NAND mode of operation or a NOR mode of operation. Finally, the array is partitionable by a user into two partitions such that one partition operates only in the NAND mode while the other partition operates only in a NOR mode.Type: GrantFiled: January 7, 2004Date of Patent: November 22, 2005Assignee: Integrated Memory Technologies, Inc.Inventors: Ching-Shi Jenq, Tien-Ler Lin
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Patent number: 6764905Abstract: A scalable flash EEPROM cell having a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate is a spacer having a bottom surface positioned over a second portion of the channel and is insulated therefrom. The floating gate has two side surfaces extending from the bottom surface. A control gate is over the floating gate and includes a first portion that is adjacent the floating gate first side surface, and a second portion adjacent the floating gate second side surface.Type: GrantFiled: July 9, 2003Date of Patent: July 20, 2004Assignee: Integrated Memory Technologies, Inc.Inventors: Ching-Shi Jeng, Ching Dong Wang
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Patent number: 6621115Abstract: A scalable flash EEPROM cell having a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate is a spacer having a bottom surface positioned over a second portion of the channel and is insulated therefrom. The floating gate has two side surfaces extending from the bottom surface. A control gate is over the floating gate and includes a first portion that is adjacent the floating gate first side surface, and a second portion adjacent the floating gate second side surface.Type: GrantFiled: November 6, 2001Date of Patent: September 16, 2003Assignee: Integrated Memory Technologies, Inc.Inventors: Ching-Shi Jenq, Ching Dong Wang
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Patent number: 6614715Abstract: A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, and a plurality of page buffers grouped in a plurality of sub-pages. Each page buffer is connected to corresponding bit lines through a first column decoder circuit and connected to one corresponding output buffer through a second column decoder circuit. This construction allows the peripheral control circuits to clock out data stored in page buffers of a first sub-page into output buffers while latching bit line data into page buffers of a second sub-page. Therefore, this architecture is able to perform read and update the page buffer data of different sub-pages simultaneously. Two sets of address registers are used to store the starting and the end address for programming. During programming, only sub-pages located between the starting and end address will be programmed successively.Type: GrantFiled: July 25, 2002Date of Patent: September 2, 2003Assignee: Integrated Memory Technologies, Inc.Inventors: Cheng-Chung Tsao, Tien-ler Lin
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Patent number: 6556508Abstract: A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, and a plurality of page buffers grouped in a plurality of sub-pages. Each page buffer is connected to corresponding bit lines through a first column decoder circuit and connected to one corresponding output buffer through a second column decoder circuit. This construction allows the peripheral control circuits to clock out data stored in page buffers of a first sub-page into output buffers while latching bit line data into page buffers of a second sub-page. Therefore, this architecture is able to perform read and update the page buffer data of different sub-pages simultaneously. Two sets of address registers are used to store the starting and the end address for programming. During programming, only sub-pages located between the starting and end address will be programmed successively.Type: GrantFiled: July 25, 2002Date of Patent: April 29, 2003Assignee: Integrated Memory Technologies, Inc.Inventors: Cheng-Chung Tsao, Tien-ler Lin
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Patent number: 6507514Abstract: An integrated circuit chip suitable for use in either a single chip packaged configuration or a multi-chip packaged configuration is disclosed. The chip has a conventional memory circuit portion and a control circuit portion. In operation as a single chip packaged configuration, the control circuit portion is inactive. In a multi-chip packaged configuration, the control circuit serves to prolong the activation of the currently addressed memory chip, while delaying the activation of the memory chip which is to be addressed in the next memory address cycle.Type: GrantFiled: October 10, 2001Date of Patent: January 14, 2003Assignee: Integrated Memory Technologies, Inc.Inventors: Cheng-Chung Tsao, Tien-Ler Lin
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Patent number: 6496415Abstract: A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, a plurality of page latches 18L, and a plurality of Quick Current Level Translators (QCLT). Each QCLT is connected to and is shared by a plurality of bit lines (32 in the preferred embodiment) through a first column decoder 44/46U and is also connected to a plurality of page latches through a second column decoder 46L. Each page latch is connected to one corresponding output buffer through a third column decoder circuit 38/40/42. The page latches are grouped in a plurality of sub-pages. The QCLT performs high speed and high accuracy current-mode comparison and converts the result of comparison into binary codes. These codes are stored in Q-latches 36U-2. The QCLT functions as a current-mode analog-to-digital converter (ADC) which converts the memory cell current to binary codes.Type: GrantFiled: November 27, 2001Date of Patent: December 17, 2002Assignee: Integrated Memory Technologies, Inc.Inventor: Cheng-Chung Tsao
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Patent number: 6469955Abstract: A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, and a plurality of page buffers grouped in a plurality of sub-pages. Each page buffer is connected to corresponding bit lines through a first column decoder circuit and connected to one corresponding output buffer through a second column decoder circuit. This construction allows the peripheral control circuits to clock out data stored in page buffers of a first sub-page into output buffers while latching bit line data into page buffers of a second sub-page. Therefore, this architecture is able to perform read and update the page buffer data of different sub-pages simultaneously. Two sets of address registers are used to store the starting and the end address for programming. During programming, only sub-pages located between the starting and end address will be programmed successively.Type: GrantFiled: November 21, 2000Date of Patent: October 22, 2002Assignee: Integrated Memory Technologies, Inc.Inventors: Cheng-Chung Tsao, Tien-ler Lin
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Patent number: 6377507Abstract: A nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows, a plurality of word lines, a plurality of bit lines, a plurality of output buffers, a plurality of page latches 18L, and a plurality of Quick Current Level Translators (QCLT). Each QCLT is connected to and is shared by a plurality of bit lines (32 in the preferred embodiment) through a first column decoder 44/46U and is also connected to a plurality of page latches through a second column decoder 46L. Each page latch is connected to one corresponding output buffer through a third column decoder circuit 38/40/42. The page latches are grouped in a plurality of sub-pages. The QCLT performs high speed and high accuracy current-mode comparison and converts the result of comparison into binary codes. These codes are stored in Q-latches 36U-2. The QCLT functions as a current-mode analog-to-digital converter (ADC) which converts the memory cell current to binary codes.Type: GrantFiled: April 6, 2001Date of Patent: April 23, 2002Assignee: Integrated Memory Technologies, Inc.Inventor: Cheng-Chung Tsao
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Patent number: 6259625Abstract: A method and an apparatus is provided to decrease the erase current level by subdividing the memory array into small segments and cycle through complete address space sequentially during the chip erase operation. Therefore, the transient erase current is proportionally reduced and is still within the current driving capability of an on-chip pump when a smaller memory segment is chosen. Furthermore, a chip erase operation can be divided into two stages. During the first stage of the chip erase operation, chip erase current is high and is supplied through a VCC power supply that can deliver a high current, but not a high enough voltage to ensure sufficient erasure of memory cells. During the second stage of the chip erase operation, the erase current is much lower and is supplied through an on-chip charge pump that can deliver much higher voltage than the VCC power supply to ensure the memory cell array is properly erased.Type: GrantFiled: June 7, 2000Date of Patent: July 10, 2001Assignee: Integrated Memory Technologies, Inc.Inventor: Tien L. Lin
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Patent number: 6232185Abstract: A method for making a non-volatile memory cell having a select gate, a floating gate and a control gate of the completely self-aligned type, partially self-aligned type and non-aligned type is disclosed.Type: GrantFiled: May 15, 2000Date of Patent: May 15, 2001Assignee: Integrated Memory Technologies, Inc.Inventor: Ching D. Wang
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Patent number: 6134144Abstract: A novel flash memory array has an array of memory cells with each memory cell being of a floating gate memory transistor with a plurality of terminals. The memory cells are arranged in a plurality of rows and a plurality of columns, with a word line connecting the memory cells in the same row. A row decoder is positioned adjacent one side of the memory array and is connected to the plurality of word lines for receiving an address signal and for supplying a low voltage signal. A plurality of programming lines are connected to the plurality of rows of memory cells of the array with a programming line connected to the memory cells in the same row. The plurality of programming lines are collinear with but spaced apart from the plurality of word lines and extending only to the row decoder.Type: GrantFiled: September 15, 1998Date of Patent: October 17, 2000Assignee: Integrated Memory Technologies, Inc.Inventors: Tien L. Lin, Ben Yau Sheen
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Patent number: 6134149Abstract: A method and an apparatus is provided to decrease the erase current level by subdividing the memory array into small segments and cycle through complete address space sequentially during the chip erase operation. Therefore, the transient erase current is proportionally reduced and is still within the current driving capability of an on-chip pump when a smaller memory segment is chosen. Furthermore, a chip erase operation can be divided into two stages. During the first stage of the chip erase operation, chip erase current is high and is supplied through a V.sub.CC power supply that can deliver a high current, but not a high enough voltage to ensure sufficient erasure of memory cells. During the second stage of the chip erase operation, the erase current is much lower and is supplied through an on-chip charge pump that can deliver much higher voltage than the V.sub.CC power supply to ensure the memory cell array is properly erased.Type: GrantFiled: March 1, 1999Date of Patent: October 17, 2000Assignee: Integrated Memory Technologies, Inc.Inventor: Tien L. Lin
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Patent number: 6057575Abstract: A scalable flash EEPROM cell has a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate has a first edge and a second edge with a first portion over the select gate and insulated therefrom, and a second portion over a second portion of the channel and over the source, and is between the select gate and the source. A control gate is over the floating gate and is insulated therefrom and has a first edge and a second edge aligned with the first edge and the second edge of the floating gate.Type: GrantFiled: July 2, 1998Date of Patent: May 2, 2000Assignee: Integrated Memory Technologies, Inc.Inventor: Ching-Shi Jenq
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Patent number: 5912843Abstract: A scalable flash EEPROM cell has a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate has a first portion over the select gate and insulated therefrom, and a second portion over a second portion of the channel and over the source, and is between the select gate and the source. A control gate is over the floating gate and is insulated therefrom. A memory array using this memory cell is also disclosed.Type: GrantFiled: January 31, 1997Date of Patent: June 15, 1999Assignee: Integrated Memory Technologies, Inc.Inventor: Ching-Shi Jeng
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Patent number: 5886887Abstract: A voltage multiplier has a number of electrically-like stages. Each of the stages receives two input signals and a pump signal. The stage has an MOS transistor with a first source/drain region and a second source/drain region and a gate. Each stage also has means for receiving a pump signal and for separately pumping the first source/drain region and the gate of the first transistor by the pump signal. The two input signals are supplied to the first source/drain region and the gate of the first transistor, respectively. A first output signal is supplied from the second source/drain region of the first transistor, and from the first source/drain region of the first transistor. A voltage signal is supplied as the input signal of the first stage and a clock signal having a first phase is supplied to the first stage as the pump signal of the first stage.Type: GrantFiled: March 26, 1998Date of Patent: March 23, 1999Assignee: Integrated Memory Technologies, Inc.Inventor: Ching-Shi Jenq
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Patent number: 5856943Abstract: A scalable flash EEPROM cell has a semiconductor substrate with a drain and a source and a channel therebetween. A select gate is positioned over a portion of the channel and is insulated therefrom. A floating gate has a first portion over the select gate and insulated therefrom, and a second portion over a second portion of the channel and over the source, and is between the select gate and the source. A control gate is over the floating gate and is insulated therefrom. A memory array using this memory cell is also disclosed.Type: GrantFiled: March 27, 1997Date of Patent: January 5, 1999Assignee: Integrated Memory Technologies, Inc.Inventor: Ching-Shi Jeng