Abstract: A dead time regulating apparatus is used in a switch mode power system. The apparatus, comprises a power MOSFET circuit with PMOS and NMOS devices. Driving means is connected for driving and for turning-on a delay in the MOSFETs. A time delay detecting means is connected for detecting dead time during MOSFET turn on and a pulse width comparing means is connected for receiving dead time signals and synchronous pulses for generating control signals. The control signals are directed to the driver means respectively for adjusting turn-on delays. The method of the invention provides precise dead time control in the MOSFET devices. The circuit drives the two MOSFET devices such that there is precise control of the dead time during on-off switching.