Abstract: This invention provides a method for bit detection of the GFSK signals at the receiver end. The bit detection is done digitally after the carrier is removed. It employs differential detection incorporated with decision feedback, which uses previous one (so-called on-bit differential detection), or two (so-called two-bit differential detection) bits as correcting information. In addition, synchronization for bit timing and frequency offset resulted from clocks between the transmitter and receiver are also performed with or without preamble as prior information. If preamble is available, the bit timing and frequency-offset bias are estimated from the preamble, which is the case of this present invention. If preamble is not available, this information is estimated directly from the unknown received signals. Once the information about the bit timing and frequency offset is obtained, it is used for the following bit detection.

Abstract: A channel noise estimating method and apparatus applied to a multi-carrier system are disclosed, where data symbols received by a receiving unit are applied to reconstruct the original transmitted data symbols. The reconstructing process is performed by either a soft decision or a hard decision technique to simulate the original transmitted data symbols. These simulated transmitted data symbols in company with the received data symbols are further applied to calculate the channel noise based on an LMS algorithm.

Abstract: A layout of a wireless communication circuit on a printed circuit board (PCB), which is a rectangular board wherein a first side is a Y-axis and a second side is an X-axis. The layout has a first antenna located at a corner between the first side and the second side. An antenna switch and a first filter are located at middle y-coordinate and a X-coordinate. A RF integrated circuit (RFIC) is located after the first filter. A first regulator is located near the second side and higher than the RFIC. A media access control (MAC) is located at about a middle y-coordinate and higher than the first regulator. An oscillator is located at a corner between the second side and the third side. A second regulator is located near the fourth side and above the first regulator. A power amplifier is located near the fourth side above the RFIC. A second filter and a transmitting/receiving (T/R) switch are located before the power amplifier. A second antenna is located at a corner between the first side and the fourth side.

Abstract: A digital-to-analog converter (DAC) for use in high-speed wireless communications. The DAC of the invention comprises a plurality of current steering cells to bi-directionally provide a differential current output. When the DAC sets the differential current output to zero for example, each of the current steering cells establishes dummy branches between a pair of current sources and thereby prevents the current sources from floating. This in turn enables the DAC to operate with a higher update rate.

Abstract: A differential to single-ended converter, which is composed of a transconductance amplifier, a current mirror and buffer circuit and a transimpedance stage, is disclosed. A differential voltage signal is provided to the inputs of the transconductance amplifier and converted to a differential current signal. The current mirror and buffer circuit serves as a differential to single-ended current conveyer and isolates the transconductance stage and the following transimpedance stage. Finally, the single-ended current signal is provided to the input of the transimpedance stage and converted to a single-ended current signal.

Abstract: A method is directed to recovering a digital data content in a communication system, wherein the digital data content has been converted into an analog signal based on a primary clock, at a transmitter for transmitting to a receiver. The method comprises receiving the analog signal by the receiver. The analog signal is converted into a digital signal, based on a clock of the receiver. The digital signal is interpolated at the desired interpolation point, if digital signal in time has been shifted by an amount equal to or larger than a predetermined time length. The interpolated digital signal is recovered back to the digital data content, with the assist of an estimated channel impulse response. The channel impulse response is retrained every time when the interpolation point is significantly changed.

Abstract: A preferred embodiment of the invention advantageously provides a method for integrating a plurality of radio systems in a unified transceiver structure and the device of the same. According to this general embodiment of the invention, all components for the necessary communication protocols of a device are determined by selecting the operation ranges of the components and designing a mechanism to adjust the operation parameters of the shared components for conforming to the utilized communications system. Therefore, only one radio frequency (RF) module is required for a communications device having a plurality of communication systems. An end user can advantageously carry a single and compact wireless device for various communications systems.

Abstract: A frequency offset estimation based on state-based differential accumulation and the device thereof are disclosed. The concept of the sate-based operation is introduced by mathematical derivations. The knowledge of received data symbols and timing is utilized. Then the detailed operations are also given by both equations and conceptual descriptions. It is unnecessary to estimate the channel jointly or concurrently, while the differential operation over the received samples of the same state is performed. Such operation is obviously much simpler and easier to implement in VLSI than all the other techniques.